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hc05 MC68HC05F4/d MC68HC05F4 mc68hc705f4 technical data MC68HC05F4 technical data 05f4book page 1 tuesday, august 5, 1997 1:10 pm
05f4book page 2 tuesday, august 5, 1997 1:10 pm
1 2 3 4 5 6 7 8 9 10 11 12 a introduction modes of operation and pin descriptions memory and registers parallel input/output ports core timer 16-bit programmable timer dtmf/melody generator resets and interrupts cpu core and instruction set electrical specifications mechanical data ordering information features specific to the mc68hc705f4 tpg 1 05f4book page 3 tuesday, august 5, 1997 1:10 pm
1 2 3 4 5 6 7 8 9 10 11 12 a introduction modes of operation and pin descriptions memory and registers parallel input/output ports core timer 16-bit programmable timer dtmf/melody generator resets and interrupts cpu core and instruction set electrical specifications mechanical data ordering information features specific to the mc68hc705f4 tpg 2 05f4book page 4 tuesday, august 5, 1997 1:10 pm
customer feedback questionnaire (MC68HC05F4/d) motorola wishes to continue to improve the quality of its documentation. we would welcome your feedback on the publication you have just received. having used the document, please complete this card (or a photocopy of it, if you prefer). 1. how would you rate the quality of the document? check one box in each category. excellent poor excellent poor organization oooo tables oooo readability oooo table of contents oooo understandability oooo index oooo accuracy oooo page size/binding oooo illustrations oooo overall impression oooo comments: 2. what is your intended use for this document? if more than one option applies, please rank them (1, 2, 3). selection of device for new application o other o please specify: system design o training purposes o 3. how well does this manual enable you to perform the task(s) outlined in question 2? completely not at all comments: oooo 4. how easy is it to ?d the information you are looking for? easy dif?ult comments: oooo 5. is the level of technical detail in the following sections suf?ient to allow you to understand how the device functions? too little detail too much detail 6. have you found any errors? if so, please comment: 7. from your point of view, is anything missing from the document? if so, please say what: ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ?cut along this line to remove section 1 introduction section 2 modes of operation and pin descriptions section 3 memory and registers section 4 parallel input/output ports section 5 core timer section 6 16-bit programmable timer section 7 dtmf/melody generator section 8 resets and interrupts section 9 cpu core and instruction set section 10 electrical specifications section 11 mechanical data section 12 ordering information appendixa features specific to the mc68hc705f4 125 05f4book page v tuesday, august 5, 1997 1:10 pm
13. currently there is some discussion in the semiconductor industry regarding a move towards providing data sheets in electron ic form. if you have any opinion on this subject, please comment. 14. we would be grateful if you would supply the following information (at your discretion), or attach your card. name: phone no: position: fax no: department: company: address: thank you for helping us improve our documentation, technical publications manager, motorola ltd., scotland . ?cut along this line to remove ?third fold back along this line 8. how could we improve this document? 9. how would you rate motorolas documentation? excellent poor ?in general oooo ?against other semiconductor suppliers oooo 10. which semiconductor manufacturer provides the best technical documentation? 11. which company (in any ?ld) provides the best technical documentation? 12. how many years have you worked with microprocessors? less than 1 year o 1? years o 3? years o more than 5 years o ?second fold back along this line ? finally, tuck this edge into opposite ?p " by air mail par avion ne pas affranchir ibrs number phq-b/207/g ccri numero phq-b/207/g reponse payee grande-bretagne motorola ltd., colvilles road, kelvin industrial estate, east kilbride, g75 8br. great britain. f.a.o. technical publications manager (re: MC68HC05F4/d) no stamp required ?first fold back along this line semiconductor products sector 126 05f4book page vi tuesday, august 5, 1997 1:10 pm
all products are sold on motorola? terms & conditions of supply. in ordering a product covered by this document the customer agrees to be bound by those terms & conditions and nothing contained in this document constitutes or forms part of a contract (with the exception of the contents of this notice). a copy of motorola? terms & conditions of supply is availab le on request. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation consequential or incidental damages. ?ypical?parameters can and do vary in different applications. all operating parameters, including ?ypicals? must be validated for each customer application by customer? technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer.
tpg 4 conventions where abbreviations are used in the text, an explanation can be found in the glossary, at the back of this manual. register and bit mnemonics are de?ed in the paragraphs describing them. an overbar is used to designate an active-low signal, eg: reset . unless otherwise stated, shaded cells in a register diagram indicate that the bit is either unused or reserved; ? is used to indicate an unde?ed state (on reset). 05f4book page 6 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola i table of contents figure number page number title table of contents 1 introduction 1.1 features.............................................................................................................1? 1.2 mask options for the MC68HC05F4 ..................................................................1? 2 modes of operation and pin descriptions 2.1 single-chip mode ...............................................................................................2? 2.2 low power modes..............................................................................................2? 2.2.1 stop mode .................................................................................................2? 2.2.2 wait mode ..................................................................................................2? 2.3 system options register .....................................................................................2? 2.4 pin descriptions .................................................................................................2? 2.4.1 vdd and vss ..............................................................................................2? 2.4.2 irq ..............................................................................................................2? 2.4.3 reset .........................................................................................................2? 2.4.4 pa0?a7/keyboard interrupt ........................................................................2? 2.4.5 pb0?b7 .....................................................................................................2? 2.4.6 pc0?c7 .....................................................................................................2? 2.4.7 pd0?d7 .....................................................................................................2? 2.4.8 tcap1, tcmp1, tcap2, tcmp2 ................................................................2? 2.4.9 tno and tnx ..............................................................................................2? 2.4.10 osc1 and osc2 .........................................................................................2? 2.4.10.1 crystal ....................................................................................................2? 2.4.10.2 external clock .........................................................................................2? tpg 5 05f4book page i tuesday, august 5, 1997 1:10 pm
motorola -ii MC68HC05F4 table of contents 3 memory and registers 3.1 registers ...........................................................................................................3? 3.2 ram ..................................................................................................................3? 3.3 rom ..................................................................................................................3? 3.4 bootloader rom................................................................................................3? 3.5 eeprom ...........................................................................................................3? 3.5.1 eeprom programming register ..................................................................3? 3.5.2 programming and erasing procedures.........................................................3? 3.5.3 sample eeprom programming sequence .................................................3? 4 parallel input/output ports 4.1 input/output programming .................................................................................4? 4.2 port a.................................................................................................................4? 4.2.1 keyboard interrupt .......................................................................................4? 4.2.1.1 key control register ................................................................................4? 4.3 port b.................................................................................................................4? 4.4 port c ................................................................................................................4? 4.5 port d ................................................................................................................4? 4.6 port registers .....................................................................................................4? 4.6.1 port data registers (ports a, b, c and d).....................................................4? 4.6.2 data direction registers (ddra, ddrb, ddrc and ddrd) .......................4? 5 core timer 5.1 real time interrupts (rti) ..................................................................................5? 5.2 core timer registers ...........................................................................................5? 5.2.1 core timer control and status register (ctcsr)..........................................5? 5.2.2 core timer counter register (ctcr).............................................................5? 5.3 computer operating properly (cop) watchdog timer ........................................5? 5.4 core timer during wait .....................................................................................5? 5.5 core timer during stop ....................................................................................5? 6 16-bit programmable timer 6.1 counter..............................................................................................................6? 6.1.1 counter register and alternate counter register ...........................................6? 6.2 timer control and status ....................................................................................6? 6.2.1 timer control registers 1 and 2 (tcr1 and tcr2) ......................................6? 6.2.2 timer status register (tsr) .........................................................................6? 6.3 input capture .....................................................................................................6? tpg 6 05f4book page ii tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola -iii table of contents 6.3.1 input capture register 1 (icr1) ....................................................................6? 6.3.2 input capture register 2 (icr2) ..................................................................6?0 6.4 output compare ...............................................................................................6?1 6.4.1 output compare register 1 (ocr1)............................................................6?1 6.4.2 output compare register 2 (ocr2)............................................................6?2 6.5 timer during stop mode................................................................................6?3 6.6 timer during wait mode.................................................................................6?3 6.7 timer state diagrams .......................................................................................6?3 7 dtmf/melody generator 7.1 introduction ........................................................................................................7? 7.1.1 features .......................................................................................................7? 7.2 functional description........................................................................................7? 7.3 dmg registers ...................................................................................................7? 7.3.1 row and column frequency control registers ...............................................7? 7.3.2 tone control register (tncr) .......................................................................7? 7.4 operation of the dmg........................................................................................7? 7.5 dmg during wait mode....................................................................................7? 7.6 dmg during stop mode...................................................................................7? 8 resets and interrupts 8.1 resets ...............................................................................................................8? 8.1.1 power-on reset .............................................................................................8? 8.1.2 reset pin ...................................................................................................8? 8.1.3 illegal address reset.....................................................................................8? 8.1.4 computer operating properly (cop) reset ...................................................8? 8.1.5 low voltage reset .........................................................................................8? 8.2 interrupts ...........................................................................................................8? 8.2.1 interrupt priorities .........................................................................................8? 8.2.2 non-maskable software interrupt (swi) .......................................................8? 8.2.3 maskable hardware interrupts......................................................................8? 8.2.3.1 real time and core timer (ctimer) interrupts .......................................8? 8.2.3.2 programmable 16-bit timer interrupt.......................................................8? 8.2.3.3 keyboard interrupt ..................................................................................8? 8.2.3.4 low voltage interrupt ..............................................................................8? 8.2.3.5 system options register..........................................................................8? 8.2.4 hardware controlled interrupt sequence ......................................................8? tpg 7 05f4book page iii tuesday, august 5, 1997 1:10 pm
motorola -iv MC68HC05F4 table of contents 9 cpu core and instruction set 9.1 registers ...........................................................................................................9? 9.1.1 accumulator (a) ...........................................................................................9? 9.1.2 index register (x) .........................................................................................9? 9.1.3 program counter (pc)..................................................................................9? 9.1.4 stack pointer (sp)........................................................................................9? 9.1.5 condition code register (ccr).....................................................................9? 9.2 instruction set ....................................................................................................9? 9.2.1 register/memory instructions ......................................................................9? 9.2.2 branch instructions ......................................................................................9? 9.2.3 bit manipulation instructions ........................................................................9? 9.2.4 read/modify/write instructions.....................................................................9? 9.2.5 control instructions ......................................................................................9? 9.2.6 tables...........................................................................................................9? 9.3 addressing modes.............................................................................................9? 9.3.1 inherent........................................................................................................9? 9.3.2 immediate ....................................................................................................9? 9.3.3 direct ...........................................................................................................9? 9.3.4 extended....................................................................................................9?2 9.3.5 indexed, no offset ......................................................................................9?2 9.3.6 indexed, 8-bit offset ...................................................................................9?2 9.3.7 indexed, 16-bit offset .................................................................................9?2 9.3.8 relative ......................................................................................................9?3 9.3.9 bit set/clear ................................................................................................9?3 9.3.10 bit test and branch.....................................................................................9?3 10 electrical specifications 10.1 maximum ratings .............................................................................................10? 10.2 thermal characteristics and power considerations .........................................10? 10.3 dc electrical characteristics ............................................................................10? 10.4 control timing ..................................................................................................10? 10.5 dc levels for low voltage reset and lvi .......................................................10? 10.6 electrical speci?ations for dtmf/melody generator ......................................10? 10.7 eeprom additional information......................................................................10? 11 mechanical data tpg 8 05f4book page iv tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola -v table of contents 12 ordering information 12.1 eproms..........................................................................................................12? 12.2 veri?ation media ............................................................................................12? 12.3 rom veri?ation units(rvu)............................................................................12? a features specific to the mc68hc705f4 a.1 features................................................................................................................ a-1 a.2 memory and registers........................................................................................... a-1 a.2.1 registers......................................................................................................... a-1 a.2.2 eprom ........................................................................................................... a-5 a.2.2.1 eprom programming register (prog) .................................................... a-5 a.2.2.2 eprom programming operation ............................................................... a-6 a.3 electrical speci?ations ........................................................................................ a-6 a.3.1 eprom characteristics ................................................................................... a-6 tpg 9 05f4book page v tuesday, august 5, 1997 1:10 pm
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MC68HC05F4 motorola vii list of figures figure number page number title list of figures 1-1 MC68HC05F4 block diagram .................................................................................. 1? 2-1 stop and wait ?wcharts ..................................................................................... 2? 2-2 oscillator connections ............................................................................................. 2? 3-1 MC68HC05F4 memory map ................................................................................... 3? 4-1 structure of port with keyboard interrupt ................................................................. 4? 4-2 standard i/o port structure...................................................................................... 4? 5-1 core timer block diagram......................................................................................... 5? 6-1 16-bit programmable timer block diagram ............................................................... 6? 6-2 timer state timing diagram for reset ...................................................................... 6?4 6-3 timer state timing diagram for input capture ......................................................... 6?4 6-4 timer state timing diagram for output compare ..................................................... 6?5 6-5 timer state timing diagram for timer over?w........................................................ 6?5 7-1 dtmf/melody generator (dmg) block diagram....................................................... 7? 8-1 interrupt ?wchart.................................................................................................... 8? 9-1 programming model ................................................................................................ 9? 9-2 stacking order ......................................................................................................... 9? 11-1 44-pin qfp pinout ................................................................................................. 11? 11-2 44-pin qfp mechanical dimensions...................................................................... 11? 11-3 28-pin pdip/soic pinout....................................................................................... 11? 11-4 28-pin soic mechanical dimensions .................................................................... 11? 11-5 mechanical dimensions for 28-pin pdip package ................................................. 11? a-1 mc68hc705f4 block diagram ................................................................................. a-2 a-2 mc68hc705f4 memory map .................................................................................. a-3 tpg 11 05f4book page vii tuesday, august 5, 1997 1:10 pm
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MC68HC05F4 motorola ix list of tables figure number page number title list of tables 3-1 register outline........................................................................................................ 3? 3-2 erase modes ........................................................................................................... 3? 4-1 i/o pin states ........................................................................................................... 4? 5-1 example rti periods ............................................................................................... 5? 5-2 minimum cop reset times....................................................................................... 5? 7-1 bit description for dtmf generation........................................................................ 7? 7-2 bit description for melody generator........................................................................ 7? 7-3 mode of operation for dmg ..................................................................................... 7? 7-4 effect of tone generation on dmg ........................................................................... 7? 8-1 vector address for interrupts and reset.................................................................... 8? 9-1 mul instruction........................................................................................................ 9? 9-2 register/memory instructions.................................................................................. 9? 9-3 branch instructions .................................................................................................. 9? 9-4 bit manipulation instructions.................................................................................... 9? 9-5 read/modify/write instructions ................................................................................ 9? 9-6 control instructions.................................................................................................. 9? 9-7 instruction set .......................................................................................................... 9? 9-8 m68hc05 opcode map.......................................................................................... 9?1 10-1 maximum ratings ................................................................................................... 10? 10-2 package thermal characteristics............................................................................ 10? 10-3 dc electrical characteristics (vdd = 5.0 v)........................................................... 10? 10-4 dc electrical characteristics (vdd = 2.7 v)........................................................... 10? 10-5 control timing (v dd = 5v)...................................................................................... 10? 10-6 control timing (v dd = 2.7v)................................................................................... 10? 10-7 dc levels for low voltage reset and lvi ................................................................. 10? 10-8 sine wave tones at tno ........................................................................................ 10? 10-9 square wave tones at tno.................................................................................... 10? 10-10 tonex at tnx output ........................................................................................... 10? 10-11 eeprom additional information............................................................................ 10? 12-1 mc order numbers................................................................................................. 12? a-1 register outline......................................................................................................... a-4 a-2 eprom characteristics ............................................................................................ a-6 tpg 13 05f4book page ix tuesday, august 5, 1997 1:10 pm
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MC68HC05F4 motorola 1-1 introduction 1 1 introduction the MC68HC05F4 is a member of the m68hc05 family of hcmos microcomputers. in addition to 4k bytes of rom, the MC68HC05F4 contains 256 bytes of ram and 256 bytes of eeprom. the on-board features of this device make it particularly suited to highly integrated and cost effective telephone handsets. the timer and dtmf generator allow for both pulse and tone dialling; in addition to telephone set-up parameters and features such as last number redial, the eeprom can typically store up to 12 telephone numbers of 20 digits, even after power has been removed from the circuit; the keyboard interrupt facility permits a direct interface to a telephone keypad. in addition to the high level of integration achieved, careful attention has also been paid to the low-power and low-voltage performance of the MC68HC05F4, which is of major importance in many telecommunications applications. the mc68hc705f4 is an eprom version of the MC68HC05F4, with the user rom replaced by 8kbytes of eprom. all references to the MC68HC05F4 apply equally to the mc68hc705f4, unless otherwise noted. tpg 15 05f4book page 1 tuesday, august 5, 1997 1:10 pm
motorola 1-2 MC68HC05F4 introduction 1 1.1 features fully static design featuring the industry-standard m68hc05 cpu core 3840 bytes of user rom, plus 16 bytes for vectors 256 bytes of ram 256 bytes of user eeprom dtmf/melody generator 16-bit programmable timer with two input captures and two output compares 15 stage multipurpose core timer with timer over?w, real time interrupt and cop watchdog cop watchdog timer (mask option) power saving stop and wait modes i/o lines (8 with high-voltage, open-drain outputs) 44 qfp con?uration ?total of 32 dedicated bidirectional i/o pins 28 soic/pdip con?uration ?total of 16 dedicated bidirectional i/o pins keyboard interrupt facility on eight of the i/o lines hardware interrupt with edge or edge-and-level sensitive interrupt trigger on-chip oscillator on-chip low voltage detection circuit two selectable bus frequencies power-on and power-off resets; low voltage detection circuitry (eeprom) available in 44-pin qfp package, 28-pin soic package and 28-pin pdip package (ports c and d not available in 28-pin packages) 1.2 mask options for the MC68HC05F4 there are three mask options available on the MC68HC05F4: stop instruction ?enable/disable, low voltage reset ?enable/disable, and cop watchdog timer ?enable/disable. these options are programmed during fabrication and must be speci?d by the customer at the time of ordering. tpg 16 05f4book page 2 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 1-3 introduction 1 figure 1-1 MC68HC05F4 block diagram pd7 pd6 pd5 pd4 pd2 pd1 pd0 pd3 port d ? dtmf & 16-bit timer tcmp2 tcap2 tcmp1 tcap1 port b port a port c ? pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 vdd vss 256 bytes user eeprom 256 bytes ram m68hc05 cpu keyboard interrupt 240 bytes bootloader rom 3840 bytes user rom 16 bytes user vectors core timer cop melody generator osc1 osc2 ceramic oscillator and divider reset irq tno tnx ? note that ports c and d are only available with the 44-pin package. tpg 17 05f4book page 3 tuesday, august 5, 1997 1:10 pm
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MC68HC05F4 motorola 2-1 modes of operation and pin descriptions 2 2 modes of operation and pin descriptions the normal operating mode of the MC68HC05F4 is single chip mode. there is also a bootloader mode, primarily for factory test purposes. in addition to these modes, there are three low power modes which may be entered and exited at will from user mode: stop, wait and data retention. 2.1 single-chip mode this is the normal user operating mode, in which the device functions as a self-contained microcomputer unit, with all on-board peripherals and i/o ports available to the user. all address and data activity occurs within the mcu. 2.2 low power modes 2.2.1 stop mode the stop instruction places the mcu in its lowest power consumption mode. in stop mode, the internal oscillator is turned off, halting all internal processing, including timer (and cop watchdog timer) operation. during stop mode, the core timer interrupt ?gs (ctof and rtif) and interrupt enable bits (tofe and rtie) in the ctcsr, as well as the 16-bit timer ?gs in register tsr and interrupt enable bits in register tcr, are cleared by internal hardware. the i-bit in the ccr is cleared to enable external interrupts. all other registers, the remaining bits in the ctcsr, and memory contents remain unaltered. all input/output lines remain unchanged. the processor can be brought out of stop mode only by an interrupt (irq , keyboard, lvi) if enabled or reset (external reset or low voltage reset ?lvr). see figure 2-1 . the stop instruction can be disables by a mask option. when disabled, the stop instruction is executed as a nop. tpg 19 05f4book page 1 tuesday, august 5, 1997 1:10 pm
motorola 2-2 MC68HC05F4 modes of operation and pin descriptions 2 2.2.2 wait mode the wait instruction places the mcu in a low power consumption mode, though it consumes more power than in stop mode. all cpu action is suspended, but the core timer and the 16-bit timer remain active. an interrupt from the core timer, 16-bit timer, irq , keyboard, lvi, if enabled, will cause the mcu to exit the wait mode. an external reset, or lvr, causes the mcu to exit the wait mode. during wait mode, the i-bit in the ccr is cleared to enable interrupts. all other registers, memory and input/output lines remain in their previous state. the dmg is still active during wait mode. see figure 2-1 . figure 2-1 stop and wait ?wcharts stop stop oscillator and all clocks; clear i-mask reset ? any interrupt ? fetch interrupt or reset vector turn on oscillator; wait t porl for stabilization ye s no no ye s wait oscillator active; stop processing; clear i-mask reset ? any interrupt ? fetch interrupt or reset vector restart processor clocks ye s no no ye s tpg 20 05f4book page 2 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 2-3 modes of operation and pin descriptions 2 2.3 system options register the MC68HC05F4 mcu contains a system options register which is located at address $11. this register is used to control the lvi and the clock system. note: the lvi uses the voltage reference of the low voltage reset (lvr) circuitry. this means that the lvi can only be used if the lvr is enabled by mask option. lvif ?low voltage interrupt ?g 1 (set) a low voltage interrupt has occurred. 0 (clear) no low voltage interrupt has occurred. lvif is a read only status bit and is set by the low voltage detection circuit, if power supply vdd falls below v lvi , provided the lvr is enabled (mask option) and the lvion and lvie bits are set. the lvif ?g is reset by clearing the lvie bit. the lvi circuit is rearmed by again setting the lvie bit. lvie ?low voltage interrupt enable 1 (set) low voltage interrupt and ?g generation is enabled. 0 (clear) low voltage interrupt and ?g generation is disabled. setting this bit enables the low voltage ?g and interrupt generation. a cpu interrupt request will then be generated whenever the lvif bit becomes set and the l-bit in the ccr is clear. lvion ?low voltage interrupt on 1 (set) power is supplied to the lvi circuitry. 0 (clear) lvi circuitry is disconnected from the power supply. setting this bit applies power to the lvi circuitry. if the lvi function is not used this bit should be cleared to save power. note: this bit must be set at least one instruction cycle before setting the lvie bit, to give the lvi circuitry time to stabilize. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset system options register (sor) $0011 lvif lvie lvion sc irq 0 0 0 0000 0000 tpg 21 05f4book page 3 tuesday, august 5, 1997 1:10 pm
motorola 2-4 MC68HC05F4 modes of operation and pin descriptions 2 sc ?system clock option 1 (set) bus clock f op equals f osc1 /4 (slow mode) 0 (clear) bus clock f op equals f osc1 /2 (normal operation) after power on reset the internal bus frequency is f osc1 /2. if the sc (system clock) bit is set, the bus frequency is reduced to f osc1 /4. however, this does not affect the dtmf generator, which continues to operate at f osc1 /2. irq ?interrupt sensitivity irq edge or level sensitivity 1 (set) irq input edge and level sensitive 0 (clear) irq input edge sensitive 2.4 pin descriptions 2.4.1 vdd and vss power is supplied to the microcomputer via these two pins. vdd is the positive supply pin and vss is the ground pin. it is in the nature of cmos designs that very fast signal transitions occur on the mcu pins. these short rise and fall times place very high short-duration current demands on the power supply. to prevent noise problems, special care must be taken to provide good power supply bypassing at the mcu. bypass capacitors should have good high-frequency characteristics and be as close to the mcu as possible. bypassing requirements vary, depending on how heavily the mcu pins are loaded. 2.4.2 irq this is an input-only pin for external interrupt sources. interrupt triggering is selected using the irq bit in the sor register, to be one of two options: either edge and level sensitive or edge sensitive only. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. tpg 22 05f4book page 4 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 2-5 modes of operation and pin descriptions 2 2.4.3 reset this active low i/o pin is used to reset the mcu. applying a logic zero to this pin forces the device to a known start-up state. an external rc-circuit can be connected to this pin to generate a power-on reset (por) if required. in this case, the time constant must be great enough (at least 100ms) to allow the oscillator circuit to stabilise. this input has an internal schmitt trigger to improve noise immunity. when a low voltage reset condition occurs internally, the reset pin provides an active-low open drain output signal that may be used to reset external hardware. other internal reset conditions are not visible at the reset pin. 2.4.4 pa0?a7/keyboard interrupt the eight i/o lines that comprise port a are con?ured as inputs during reset. port a shares its pins with the keyboard interrupt function. each line has an internal pull-up resistor. 2.4.5 pb0?b7 the eight i/o lines that comprise port b are con?ured as inputs during reset. lines pb0 and pb1 have open drain outputs, lines pb2 and pb3 have internal pull-up resistors and lines pb4?b7 have internal pull-down resistors. 2.4.6 pc0?c7 during reset, the eight i/o lines of port c are con?ured as inputs and each has an internal pull-up resistor. note: these pins are not available on the 28-pin version. 2.4.7 pd0?d7 during reset, the eight lines of port d are con?ured as inputs. as all port d pins are open drain outputs, an external pull-up resistor is needed when a pin is used as an output. note: these pins are not available on the 28-pin version. tpg 23 05f4book page 5 tuesday, august 5, 1997 1:10 pm
motorola 2-6 MC68HC05F4 modes of operation and pin descriptions 2 2.4.8 tcap1, tcmp1, tcap2, tcmp2 these four pins are connected to the 16-bit programmable timer system. tcap1 and tcap2 are the timer input capture pins. tcmp1 and tcmp2 are the output compare pins for the timer. tcmp1 and tcmp2 are open drain outputs, therefore each pin requires an external pull-up resistor when it is used as an output. 2.4.9 tno and tnx the tno output provides dual tone dtmf or melody under program control. tno is an open-drain output, and therefore requires an external pull-up resistor. the tnx output provides paci?r tones under program control. 2.4.10 osc1 and osc2 these pins provide control input for an on-chip oscillator circuit. a crystal or external clock signal connected to these pins supplies the oscillator clock. the oscillator frequency of 3.579 mhz provides the time base for the real-time clock and the dtmf/melody generator. 2.4.10.1 crystal the circuit shown in figure 2-2 (a) is recommended when using either a crystal or a ceramic resonator. figure 2-2 (d) provides the recommended capacitance and feedback resistance values. the internal oscillator is designed to interface with an at-cut parallel-resonant quartz crystal resonator in the frequency range speci?d for f osc (see section 10.4 ). use of an external cmos oscillator is recommended when crystals outside the speci?d ranges are to be used. the crystal and associated components should be mounted as close as possible to the input pins to minimize output distortion and start-up stabilization time. the manufacturer of the particular crystal being considered should be consulted for speci? information. 2.4.10.2 external clock an external clock should be applied to the osc1 input, with the osc2 pin left unconnected, as shown in figure 2-2 (c). the t oxov speci?ation (see section 10.4 ) does not apply when using an external clock input. the equivalent speci?ation of the external clock source should be used in lieu of t oxov . tpg 24 05f4book page 6 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 2-7 modes of operation and pin descriptions 2 figure 2-2 oscillator connections osc1 osc2 r p mcu c osc2 c osc1 osc1 osc2 mcu nc external clock osc1 osc2 r s c 1 l c 0 crystal 2mhz 4mhz unit r s (max) 400 75 w c 0 57pf c 1 812?f c osc1 15 e 40 15 e 30 pf c osc2 15 e 30 15 e 25 pf r p 10 10 m w q 30 000 40 000 ? (d) crystal resonator parameters (c) external clock source connections (b) crystal equivalent circuit (a) crystal resonator oscillator connections tpg 25 05f4book page 7 tuesday, august 5, 1997 1:10 pm
motorola 2-8 MC68HC05F4 modes of operation and pin descriptions 2 this page left blank intentionally tpg 26 05f4book page 8 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 3-1 memory and registers 3 3 memory and registers the MC68HC05F4 has a 16k byte memory map consisting of registers (for i/o, control and status), user ram, user rom, eeprom, bootloader rom and reset and interrupt vectors as shown in figure 3-1 . 3.1 registers all the i/o, control and status registers of the MC68HC05F4 are contained within the ?st 64 byte block of the memory map, as detailed in table 3-1 . 3.2 ram the user ram consists of 256 bytes of memory, from $0040 to $013f. this is shared with a 64 byte stack area. the stack begins at $00ff, and may extend down to $00c0. note: using the stack area for data storage or temporary work locations requires care to prevent the data from being overwritten due to stacking from an interrupt or subroutine call. 3.3 rom the user rom occupies 3840 bytes of memory, from $3000 to $3eff. in addition, there are 16 bytes of user vectors, from $3ff0 to $3fff. tpg 27 05f4book page 1 tuesday, august 5, 1997 1:10 pm
motorola 3-2 MC68HC05F4 memory and registers 3 figure 3-1 MC68HC05F4 memory map $00 port a data (porta) $0000 bootloader rom (240 bytes) user rom (3840 bytes) unused eeprom (256 bytes) ram (384 bytes) unused i/o (64 bytes) $0040 $0200 $02ff $3000 $3f00 $3ff0 $3fff MC68HC05F4 stack user vectors (16 bytes) $01 port b data (portb) $02 port c data 1 (portc) $03 port d data 1 (portd) $04 port a ddr (ddra) $05 port b ddr (ddrb) $06 port c ddr 1 (ddrc) $08 core time control/status (ctcsr) $09 core timer counter (ctcr) $0a unused $0b reserved $0c reserved $0d dtmf row fequency counter (fcr) $0e dtmf column fequency counter (fcc) $0f dtmf tone control (tncr) $10 key control (kcr) $11 system options (sor) $12e$1b unused $1c eeprom programming (eeprog) $1de$1e unused $1f reserved $20 capture 1 high (icr1h) $21 capture 1 low (icr1l) $22 compare 1 high (ocr1h) $23 compare 1 low (ocr1l) $24 capture 2 high (icr2h) $25 capture 2 low (icr2l) $26 compare 2 high (ocr2h) $27 compare 2 low (ocr2l) $28 timer counter high (cnth) $29 timer counter low (cntl) $2a alternate counter high (acnth) $2b alternate counter low (acntl) $2c timer control 1 (tcr1) $2d timer control 2 (tcr2) $2e timer status (tsr) $2fe$3f unused $07 port d ddr 1 (ddrd) $0140 $00c0 $00ff 1. not available in 28-pin package. tpg 28 05f4book page 2 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 3-3 memory and registers 3 note: for compatibility, unused bits (shaded) should always be cleared, when writing to them. (1) not available in 28-pin packages table 3-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 undetned port b data (portb) $0001 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 undetned port c data (portc) (1) $0002 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 undetned port d data (portd) (1) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 undetned port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) (1) ) $0006 0000 0000 port d data direction ((ddrd) (1) $0007 0000 0000 core timer control/status (ctcsr) $0008 ctof rtif ctofe rtie rtof rrtif rt1 rt0 uu00 0011 core timer counter (ctcr) $0009 0000 0000 $000aec dtmf row freq. control (fcr) $000d 0 0 0 fcr4 fcr3 fcr2 fcr1 fcr0 undetned dtmf column freq. control (fcc) $000e 0 0 0 fcc4 fcc3 fcc2 fcc1 fcc0 undetned dtmf tone control (tncr) $000f ms1 ms0 tger tgec tnoe 0 0 0 0000 0000 key control (kcr) $0010 kf kie 000000 0000 0000 system options (sor) $0011 lvif lvie lvion sc irq 0 0 0 0000 0000 $0012e1b eeprom programming (eeprog) $001c 0 cpen 0 er1 er0 latch eerc eepgm 0000 0000 $001de1f input capture 1 high (icr1h) $0020 (bit 15) (bit 8) undetned input capture 1 low (icr1l) $0021 undetned output compare 1 high (ocr1h) $0022 (bit 15) (bit 8) undetned output compare 1 low (ocr1l) $0023 undetned input capture 2 high (icr2h) $0024 (bit 15) (bit 8) undetned input capture 2 low (icr2l) $0025 undetned output compare 2 high (ocr2h) $0026 (bit 15) (bit 8) undetnd output compare 2 low (ocr2l) $0027 undetned timer counter high (cnth) $0028 (bit 15) (bit 8) 1111 1111 timer counter low (cntl) $0029 1111 1100 alternate counter high (acnth) $002a (bit 15) (bit 8) 1111 1111 alternate counter low (acntl) $002b 1111 1100 timer control 1 (tcr1) $002c ici1e ici2e oci1e toie co1e iedg1 iedg2 olvl1 0000 0uu0 timer control 2 (tcr2) $002d 0 0 oci2e 0 co2e 0 0 olvl2 0000 0000 timer status (tsr) $002e ic1f ic2f oc1f tof tcap1 tcap2 oc2f 0 uuuu uuu0 $002f u = undetned tpg 29 05f4book page 3 tuesday, august 5, 1997 1:10 pm
motorola 3-4 MC68HC05F4 memory and registers 3 3.4 bootloader rom the MC68HC05F4 has 240 bytes of bootloader rom, from $3f00 to $3fef. 3.5 eeprom 256 bytes of user eeprom reside at addresses $0200 to $02ff. programming or erasing the eeprom can be done by the user on a single byte basis; erasing may also be performed on a block or bulk basis. all programming or erasing is accomplished by manipulating the programming register (eeprog), located at address $001c. note: the erased state of an eeprom byte is ?ff? this means that a write forces zeros to the bits speci?d, whilst bits de?ed as ones are unchanged by a write operation. caution: there is a restriction on the use of indexed addressing for eeprom read operations. when the base address of an indexed read of an eeprom location is within the eeprom address range ($0400 to $04ff), the read may not be successful. e.g. lda (base address), x ?may not give the correct result when the base address is in the range $0400 to $04ff. however, if the base address is outwith the eeprom address range, the read operation will be successful. this restriction applies to all operations capable of using indexed addressing. 3.5.1 eeprom programming register cpen ?charge pump enable 1 (set) charge pump enabled. 0 (clear) charge pump disabled. when set, cpen enables the charge pump which produces the internal programming voltage. this bit should be set at the same time as the latch bit. the programming voltage will not be available until eepgm is set. the charge pump should be disabled when not in use. cpen is readable and writable and is cleared by reset. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eeprom programming (eeprog) $001c 0 cpen 0 er1 er0 latch eerc eepgm 0000 0000 tpg 30 05f4book page 4 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 3-5 memory and registers 3 er1, er0 ?erase select bits er1 and er0 are used to select either single byte programming or one of three erase modes: byte, block, or bulk. table 3-2 shows the mode selected for each bit con?uration. these bits are readable and writable and are cleared by reset. in byte erase mode, only the selected byte is erased. in block erase mode, a 64-byte block of eeprom is erased. the eeprom memory space is divided into four 64-byte blocks ($0200 ?$023f, $0240 ? $027f, $0280 ?$02bf and $02c0 ?$02ff) and performing a block erase on any address within a block will erase the entire block. in bulk erase mode, the entire 256 bytes of eeprom are erased. latch ?eeprom latch bit 1 (set) eeprom address and data buses are con?ured for programming. 0 (clear) eeprom address and data buses are con?ured for normal operation. when set, the latch bit con?ures the eeprom address and data buses for programming. in addition, writes to the eeprom array cause the address and data buses to be latched. this bit is readable and writable, but reads from the eeprom array are inhibited if the latch bit is set and a write to the eeprom space has taken place. when this bit is clear, address and data buses are con?ured for normal operation. reset clears this bit. eerc ?eeprom rc oscillator control 1 (set) use internal rc oscillator for eeprom. 0 (clear) use cpu clock for eeprom. when this bit is set, the eeprom memory array uses the internal rc oscillator instead of the cpu clock. after setting the eerc bit, the user should wait a time t rcon to allow the rc oscillator to stabilize. this bit is readable and writable and should be set by the user when the internal bus frequency falls below 1.5mhz. reset clears this bit. table 3-2 erase modes er1 er0 mode 0 0 program 0 1 byte erase 1 0 block erase 1 1 bulk erase tpg 31 05f4book page 5 tuesday, august 5, 1997 1:10 pm
motorola 3-6 MC68HC05F4 memory and registers 3 eepgm ?eeprom programming power enable 1 (set) programming power connected to the eeprom array. 0 (clear) programming power switched off. eepgm must be set to enable the eepgm function. when set, eepgm turns on the charge pump and enables the programming (or erasing) power to the eeprom array. when clear, this power is switched off. this will enable pulsing of the programming voltage to be controlled internally. this bit can be read at any time, but can only be written to if latch = 1, i.e. if latch is not set, then eepgm cannot be set. reset clears this bit. 3.5.2 programming and erasing procedures to program a byte of eeprom, set latch = cpen = 1, set er1 = er0 = 0, write data to the desired address and then set eepgm for a time t epgm . there are three possibilities for erasing data from the eeprom array, depending on how much data is affected. to erase a byte of eeprom, set latch = cpen = 1, set er1 = 0 and er0 = 1, write data to the desired address and then set eepgm for a time t ebyte . to erase a block of eeprom, set latch = cpen = 1, set er1 = 1 and er0 = 0, write data to any address in the block and then set eepgm for a time t eblock . to bulk erase the eeprom, set latch = cpen = 1, set er1 = er0 = 1, write data to any address in the array and then set eepgm for a time t ebulk . to terminate the programming or erase sequence, clear eepgm, wait for a time t fpv to allow the programming voltage to fall, and then clear latch and cpen to release the buses. following each erase or programming sequence, clear all programming control bits. 3.5.3 sample eeprom programming sequence the following program is an example of the eeprom programming sequence, using the timer to implement the required delay and assuming a 1 mhz bus frequency. tpg 32 05f4book page 6 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 3-7 memory and registers 3 tcsr equ $0008 timer control and status register tcnt equ $0009 timer counter register tof equ 7 tof bit of tcsr prog equ $001c eeprom program register cpen equ 6 charge pump enable bit er1 equ 4 erase select bit 1 er0 equ 3 erase select bit 0 latch equ 2 latch bit eerc equ 1 rc/osc selector bit eepgm equ 0 eeprom program bit eestart equ $0200 start address of eeprom sumpin equ $ff dummy data org $0680 start equ * bset eerc, prog select rc oscillator bsr delay rc oscillator stabilization bset cpen, prog turn on charge pump bset latch, prog enable latch bit bclr er1, prog select program (not erase) bclr er0, prog select program (not erase) lda #sumpin get data sta eestart bset eepgm, prog enable programming power jsr delay wait for programming time bclr eepgm, prog clear eepgm jsr delay wait for prog voltage to fall bclr latch, prog clear latch bclr cpen, prog disable charge pump cmp eestart verify bne out1 clc clear carry bit if no error out rts out1 sec flag an error rts *this routine gives a 15ms (+/-1ms) delay at 1 mhz bus. the same delay * routine is used in this example for simplicity, using the longest delay * time. users will want to write shorter delay routines for applications *in which speed is important. delay equ * ldx #15 count of 15 timlp bclr tof, tcsr clear tof brclr tof, tcsr wait for tof flag decx bne timlp count down to 0 rts tpg 33 05f4book page 7 tuesday, august 5, 1997 1:10 pm
motorola 3-8 MC68HC05F4 memory and registers this page left blank intentionally 3 tpg 34 05f4book page 8 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 4-1 parallel input/output ports 4 4 parallel input/output ports the MC68HC05F4 has a total of 32 i/o lines, arranged as four 8-bit ports. the i/o lines are individually programmable as either input or output, under the software control of the data direction registers. port a can also be con?ured to respond to keyboard interrupts. to avoid glitches on the output pins, data should be written to the i/o port data register before writing ones to the corresponding data direction register bits to set the pins in output mode. 4.1 input/output programming the bidirectional port lines may be programmed as inputs or outputs under software control. the direction of each pin is determined by the state of the corresponding bit in the port data direction register (ddr). each i/o port has an associated ddr. any i/o port pin is con?ured as an output if its corresponding ddr bit is set to a logic one. a pin is con?ured as an input if its corresponding ddr bit is cleared. at power-on or reset, all ddrs are cleared, thus con?uring all port pins as inputs. the data direction registers can be written to or read by the mcu. during the programmed output state, a read of the data register actually reads the value of the output data latch and not the i/o pin. the operation of the standard port hardware is shown schematically in figure 4-2 . this is further summarized in table 4-1 , which shows the effect of reading from, or writing to an i/o pin in various circumstances. note that the read/write signal shown is internal and not available to the user. tpg 35 05f4book page 1 tuesday, august 5, 1997 1:10 pm
motorola 4-2 MC68HC05F4 parallel input/output ports 4 4.2 port a port a is an 8-bit bidirectional port which is equipped with a keyboard interrupt. all eight lines have internal pull-up resistors, which are required when the port is in input mode. on reset, this port is con?ured as a standard i/o port comprising a data register and a data direction register. reset does not affect the state of the data register, but clears the data direction register, thereby returning all ports pins to input mode. writing a 1 to any ddr bit sets the corresponding port pin to output mode. as every pin con?ured as an input contributes to the keyboard interrupt, it is possible to disable a single pin by con?uring it as an output. 4.2.1 keyboard interrupt provided that the interrupt mask bit of the condition code register is cleared, the keyboard interrupt facility is enabled by setting the keyboard interrupt bit (kie) in the key control register. on detection of a high-to-low transition, the interrupt inputs pa6 and pa7 are triggered. the trigger edges of the interrupt lines, pa0?a5, can be programmed using the edg0?dg5 bits in the key control register. if one of these bits is cleared, after reset the corresponding interrupt is falling-edge sensitive. if, however, one of them is set, after reset the corresponding interrupt is rising-edge sensitive. the internal pull-up resistors of input lines, pa7?a0, are disabled, if rising-edge sensitivity is selected. when a correct transition is detected, on any of this ports pins, a keyboard interrupt request is generated, and the corresponding interrupt status ?g of the interrupt status register, irstate, is set. the interrupt status register is an 8-bit register which has the same address as porta, $0000. this register can be read if the keymux bit in the system option register is set. if kie is set, a keyboard interrupt is generated and the keyboard status ?g, kf, is set by generating the logical or of the eight interrupt state register outputs. the 8 interrupt state register ?gs can be reset in three ways: 1) completely, if the chip is reset. 2) completely, if a 1 is written to keyclr, in the system option register. 3) individually, if a 1 is written to the corresponding bit position of the interrupt state register ($00 with keymux = 1, in the system option register). tpg 36 05f4book page 2 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 4-3 parallel input/output ports 4 4.2.1.1 key control register this register contains two bits which are used to control the keyboard interrupt facility. the keyboard interrupt and ?g setting is enabled by setting the keyboard interrupt enable bit. kf ?keyboard interrupt status ?g 1 (set) a high to low transition has occurred on one of the port pins. 0 (clear) no high to low transition has occurred on any of the port pins. this bit is set when a high to low transition is detected on any of the port a pins and if kie equals one. the kf ?g is cleared by accessing the port a register. figure 4-1 structure of port with keyboard interrupt address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset key control register (kcr) $0010 kf kie 000000 0000 0000 kie bit 6, $10 ddr0 keyboard interrupt ?g and external pin pa0 ddr01 external pin pa1 ddr7 external pin pa7 request signal tpg 37 05f4book page 3 tuesday, august 5, 1997 1:10 pm
motorola 4-4 MC68HC05F4 parallel input/output ports 4 kie ?keyboard interrupt enable 1 (set) keyboard interrupt and ?g setting enabled. 0 (clear) keyboard interrupt and ?g setting disabled. an interrupt can only be generated if kie and kf are both set and the i-bit in the ccr is clear. 4.3 port b port b is an 8-bit bidirectional port which does not share any of its pins with other subsystems. the lines pb0 and pb1 have open drain outputs, pb2 and pb3 have internal pull-up resistors and lines pb4?b7 have internal pull-down resistors. reset does not affect the state of the data register, but clears the data direction register, thereby returning all port pins to input mode. writing a ? to any ddr bit sets the corresponding port pin to output mode. figure 4-2 standard i/o port structure table 4-1 i/o pin states r/w ddrn action of mcu write to/read of data bit 0 0 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch, and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in output mode. the output data latch is read. data direction register bit latched data register bit ddrn data input buffer output buffer o/p data buffer m68hc05 internal connections ddrn data i/o 100 111 0 0 tristate 0 1 tristate i/o pin output input ? ? tpg 38 05f4book page 4 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 4-5 parallel input/output ports 4 4.4 port c port c is an 8-bit bidirectional port which does not share any of its pins with other subsystems. all eight lines have internal pull-up resistors. port c is not available on the 28-pin package. reset does not affect the state of the data register, but clears the data direction register, thereby returning all port pins to input mode. writing a ? to any ddr bit sets the corresponding port pin to output mode. the port c lines have internal pull-up resistors. 4.5 port d port d is an 8-bit bidirectional port which does not share any of its pins with other subsystems. it has open drain outputs, which means when a pin is being used as an output, an external pull-up resistor is required. port d is not available on the 28-pin package. note: as the voltage at port d is driven above v dd , the protection device will begin to conduct and tend to clamp the input voltage to protect the input buffer. the voltage at which this occurs varies signi?antly from lot to lot and over the operating temperature range. at room temperature, the pin typically does not draw any current until approximately 18v. tpg 39 05f4book page 5 tuesday, august 5, 1997 1:10 pm
motorola 4-6 MC68HC05F4 parallel input/output ports 4 4.6 port registers the following sections explain in detail the individual bits in the data and control registers associated with the ports. 4.6.1 port data registers (ports a, b, c and d) each bit of port a ?port d can be con?ured as input or output via the corresponding data direction bit in the port data direction register (ddrx). reset does not affect the state of the port a ?port d data registers. 4.6.2 data direction registers (ddra, ddrb, ddrc and ddrd) writing a ? to any bit con?ures the corresponding port pin as an output; conversely, writing any bit to ? con?ures the corresponding port pin as an input. reset clears these registers, thus con?uring all port pins as inputs. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 undetned port b data (portb) $0001 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 undetned port c data (portc) $0002 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 undetned port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 undetned address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 port d data direction (ddrd) $0007 0000 0000 tpg 40 05f4book page 6 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 5-1 core timer 5 5 core timer the MC68HC05F4 has a 15-stage ripple counter called the core timer (ctimer). features of this timer are: timer over?w, power-on reset (por), real time interrupt (rti) with four selectable interrupt rates and a computer operating properly (cop) watchdog timer. figure 5-1 core timer block diagram ctof rtif ctofe rtie rtof rrtif rt1 rt0 cop watchdog timer ( ? 8 ) to reset logic over?ow detect circuit ( ? 4 ) to interrupt logic interrupt circuit rti select circuit $09 ctcr (core timer counter) $08 ctcsr (core timer control and status) cop clear internal processor clock 7-bit counter f op f op / 2 2 f op / 2 10 f op / 2 14 f op / 2 17 internal bus 8 8 8 tpg 41 05f4book page 1 tuesday, august 5, 1997 1:10 pm
motorola 5-2 MC68HC05F4 core timer 5 as shown in figure 5-1 , the timer is driven by the internal bus clock divided by four with a ?ed prescaler. this signal drives an 8-bit ripple counter. the value of this 8-bit ripple counter can be read by the cpu at any time, by accessing the ctimer counter register (ctcr) at address $09. a timer over?w function is implemented on the last stage of this counter, giving a possible interrupt at the rate of f op /1024. (the por signal (t porl ) is also derived from this register, at f op /4064.) the counter register circuit is followed by four more stages, with the resulting clock (f op /16384) driving the real time interrupt circuit. the rti circuit consists of three divider stages with a 1-of-4 selector. the output of the rti circuit is further divided by 8 to drive the cop watchdog timer circuit. the rti rate selector bits, and the rti and ctimer over?w enable bits and ?gs, are located in the ctimer control and status register (ctcsr) at location $08. ctof (core timer over?w ?g) is a clearable, read-only status bit and is set when the 8-bit ripple counter rolls over from $ff to $00. a cpu interrupt request will be generated if ctofe is set. clearing the ctof is done by writing a ? to it. writing a ? to ctof has no effect on the bits value. reset clears ctof. when ctofe (core timer over?w enable) is set, a cpu interrupt request is generated when the ctof bit is set. reset clears ctofe. the core timer counter register (ctcr) is a read-only register that contains the current value of the 8-bit ripple counter at the beginning of the timer chain. this counter is clocked at f op /4 and can be used for various functions including a software input capture. extended time periods can be attained using the ctimer over?w function to increment a temporary ram storage location thereby simulating a 16-bit (or more) counter. the power-on cycle clears the entire counter chain and begins clocking the counter. after t porl cycles, the power-on reset circuit is released, which again clears the counter chain and allows the device to come out of reset. at this point, if reset is not asserted, the timer will start counting up from zero and normal device operation will begin. when reset is asserted at any time during operation (other than por), the counter chain will be cleared. 5.1 real time interrupts (rti) the real time interrupt circuit consists of a three stage divider and a 1-of-4 selector. the clock frequency that drives the rti circuit is f op /2 14 (or f op /16384), with three additional divider stages, giving a maximum interrupt period of 4 seconds at a bus frequency (f op ) of 32khz. register details are given in section 5.2 . tpg 42 05f4book page 2 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 5-3 core timer 5 5.2 core timer registers 5.2.1 core timer control and status register (ctcsr) ctof ?core timer over?w 1 (set) core timer over?w has occurred. 0 (clear) no core timer over?w interrupt has been generated. ctof is a read-only status bit and is set when the core timer counter register rolls over from $ff to $00; an interrupt request will be generated if ctofe is set. when set, ctof may be cleared by writing a ? to rtof. rtif ?real time interrupt ?g 1 (set) a real time interrupt has occurred. 0 (clear) no real time interrupt has been generated. rtif is a read-only status bit and is set when the output of the chosen stage becomes active; an interrupt request will be generated if rtie is set. when set, the bit may be cleared by writing a ? to rrtif. reset also clears this bit. ctofe ?core timer over?w enable 1 (set) core timer over?w interrupt is enabled. 0 (clear) core timer over?w interrupt is disabled. setting this bit enables the core timer over?w interrupt. a cpu interrupt request will then be generated whenever the ctof bit becomes set and the i-bit in the ccr is clear. clearing this bit disables the core timer over?w interrupt capability. rtie ?real time interrupt enable 1 (set) real time interrupt is enabled. 0 (clear) real time interrupt is disabled. setting this bit enables the real time interrupt. a cpu interrupt request will then be generated whenever the rtif bit becomes set and the i-bit in the ccr is clear. clearing this bit disables the real time interrupt capability. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset core timer control/status (ctcsr) $0008 ctof rtif ctofe rtie rtof rrtif rt1 rt0 uu00 0011 tpg 43 05f4book page 3 tuesday, august 5, 1997 1:10 pm
motorola 5-4 MC68HC05F4 core timer 5 rtof ?reset timer over?w ?g writing a ? to this bit clears the timer over?w ?g, ctof. see ctof description. rrtif ?reset real time over?w ?g wrting a ? to this bit clears the real time interrupt ?g, rtif. see rtif description. rt1, rt0 ?real time interrupt rate select these two bits select one of four taps from the real time interrupt circuitry. reset sets both rt0 and rt1 to one, selecting the lowest periodic rate and therefore the maximum time in which to alter them if necessary. the cop reset times are also determined by these two bits. care should be taken when altering rt0 and rt1 if a timeout is imminent, or the timeout period is uncertain. if the selected tap is modi?d during a cycle in which the counter is switching, an rtif could be missed or an additional one could be generated. to avoid problems, the cop should be cleared before changing the rti taps. see table 5-1 for some example rti periods. 5.2.2 core timer counter register (ctcr) the core timer counter register is a read-only register, which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. reset clears this register. table 5-1 example rti periods rti rates at f op frequency specited rt1 rt0 division ratio 16.384 khz 447 khz 895 khz 1.789 mhz 00 2 14 1 s 36.7 ms 18.35 ms 9.17 ms 01 2 15 2 s 73.4 ms 36.7 ms 18.35 ms 10 2 16 4 s 146.8 ms 73.4 ms 36.7 ms 11 2 17 8 s 293.6 ms 146.8 ms 73.4 ms address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset core timer counter (ctcr) $0009 0000 0000 tpg 44 05f4book page 4 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 5-5 core timer 5 5.3 computer operating properly (cop) watchdog timer the cop watchdog timer function is implemented by taking the output of the rti circuit and further dividing it by eight, as shown in figure 5-1 . note that the minimum cop timeout period is seven times the rti period. this is because the cop will be cleared asynchronously with respect to the value in the core timer counter register/rti divider, hence the actual cop timeout period will vary between 7x and 8x the rti period. the minimum cop reset rates are shown in table 5-2 . the cop function is a mask option, enabled or disabled during device manufacture. if the cop circuit times out, an internal reset is generated and the normal reset vector is fetched. a cop timeout is prevented by writing a ? to bit 0 of address $3ff0. when the cop is cleared, only the ?al divide-by-eight stage is cleared (see figure 5-1 ). 5.4 core timer during wait the cpu clock halts during the wait mode, but the timer remains active. if the ctimer interrupts are enabled, then a ctimer interrupt will cause the processor to exit the wait mode. 5.5 core timer during stop the timer is cleared when going into stop mode. when stop is exited by an external interrupt or an external reset, the internal oscillator will restart, followed by an internal processor stabilization delay (t porl ). the timer is then cleared and operation resumes. table 5-2 minimum cop reset times minimum cop reset at f op frequency specited rt1 rt0 16.384 khz 447 khz 895 khz 1.789 mhz f op 0 0 7 s 256.9 ms 128.45 ms 64.19 ms 7 x rti rate 0 1 14 s 513.8 ms 256.9 ms 128.45 ms 7 x rti rate 1 0 28 s 1.03 s 513.8 s 256.9 ms 7 x rti rate 1 1 56 s 2.06 s 1.03 s 513.8 ms 7 x rti rate tpg 45 05f4book page 5 tuesday, august 5, 1997 1:10 pm
motorola 5-6 MC68HC05F4 core timer this page left blank intentionally 5 tpg 46 05f4book page 6 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 6-1 16-bit programmable timer 6 6 16-bit programmable timer the timer consists of a 16-bit read-only free-running counter, with a ?ed divide-by-four prescaler, plus the input capture/output compare circuitry. the timer can be used for many purposes including measuring pulse length of two input signals and generating two output signals. pulse lengths for both input and output signals can vary from several microseconds to many seconds. the timer is also capable of generating periodic interrupts or indicating passage of an arbitrary multiple of four cpu cycles. a block diagram is shown in figure 6-1 , and timing diagrams are shown in figure 6-2 , figure 6-3 , figure 6-4 and figure 6-5 . the timer has a 16-bit architecture, hence each speci? functional segment is represented by two 8-bit registers. these registers contain the high and low byte of that functional segment. accessing the low byte of a speci? timer function allows full control of that function; however, an access of the high byte inhibits that speci? timer function until the low byte is also accessed. the 16-bit programmable timer is monitored and controlled by a group of ?teen registers, full details of which are contained in this section. note: a problem may arise if an interrupt occurs in the time between the high and low bytes being accessed. to prevent this, the i-bit in the condition code register (ccr) should be set while manipulating both the high and low byte register of a speci? timer function, ensuring that an interrupt does not occur. 6.1 counter the key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. the prescaler gives the timer a resolution of 2 m s if the internal bus clock is 2 mhz. the counter is incremented during the low portion of the internal bus clock. software can read the counter at any time without affecting its value. tpg 47 05f4book page 1 tuesday, august 5, 1997 1:10 pm
motorola 6-2 MC68HC05F4 16-bit programmable timer 6 figure 6-1 16-bit programmable timer block diagram internal internal bus 8 output compare register 1 processor clock 8-bit buffer ? 4 high low 16-bit free-running counter counter alternate register register 1 register 2 input capture internal timer bus over?ow detect circuit edge detect tcap1 tcmp2 tcmp1 d q compare output register 2 input capture byte byte high byte low byte high byte low byte high byte low byte low byte high byte circuit 1 compare output circuit 2 compare output circuit 1 edge detect circuit 2 pin pin pin d q tsr $002e tcr1 $002c $0028 $0029 $002a $002b $0024 $0022 $0023 $0020 $0021 $0026 $0027 $0025 ic1f ic2f oc1f tof oc2f ic1ie ic2ie oc1ie toie iedg2 olvl1 iedg1 interrupt circuit input capture interrupt vector $3ff4, 5 output compare interrupt vector $3ff4, 5 over?ow interrupt vector cop watchdog counter input $3ff4, 5 tcr2 $002d oc2ie olvl2 clk clk c c reset tcap2 pin input capture interrupt vector $3ff4, 5 output compare interrupt vector $3ff4, 5 co2e co1e tpg 48 05f4book page 2 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 6-3 16-bit programmable timer 6 6.1.1 counter register and alternate counter register the double-byte, free-running counter can be read from either of two locations, $0028 ?$0029 (counter register) or $002a ?$002b (counter alternate register). a read from only the less signi?ant byte (lsb) of the free-running counter ($0029 or $002b) receives the count value at the time of the read. if a read of the free-running counter or alternate counter register ?st addresses the more signi?ant byte (msb) ($0028 or $002a), the lsb is transferred to a buffer. this buffer value remains ?ed after the ?st msb read, even if the user reads the msb several times. this buffer is accessed when reading the free-running counter or alternate counter register lsb and thus completes a read sequence of the total counter value. in reading either the free-running counter or alternate counter register, if the msb is read, the lsb must also be read to complete the sequence. if the timer over?w ?g (tof) is set when the counter register lsb is read then a read of the timer status register (tsr) will clear the ?g. the counter alternate register differs from the counter register only in that a read of the lsb does not clear tof. therefore, where it is critical to avoid the possibility of missing timer over?w interrupts due to clearing of tof, the alternate counter register should be used. the free-running counter is set to $fffc during power-on and external reset and is always a read-only register. during a power-on reset, the counter begins running after the oscillator start-up delay. because the free-running counter is 16 bits preceded by a ?ed divide-by-4 prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. tof is set when the counter over?ws (from $ffff to $0000); this will cause an interrupt if toie is set. the divide-by-4 prescaler is also reset and the counter resumes normal counting operation. all of the ?gs and enable bits remain unaltered by this operation. if access has previously been made to the high byte of the free-running counter ($0028 or $002a), then the reset counter operation terminates the access sequence. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer counter high (cnth) $0028 1111 1111 timer counter low (cntl) $0029 1111 1100 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset alternate counter high (acnth) $002a 1111 1111 alternate counter low (acntl) $002b 1111 1100 tpg 49 05f4book page 3 tuesday, august 5, 1997 1:10 pm
motorola 6-4 MC68HC05F4 16-bit programmable timer 6 6.2 timer control and status the various functions of the timer are monitored and controlled using the timer control and status registers described below. 6.2.1 timer control registers 1 and 2 (tcr1 and tcr2) the two timer control registers tcr1 and tcr2 ($002c and $002d) are used to enable the input captures (ic1ie and ic2ie), output compares (oc1ie and oc2e), and timer over?w (toie) functions as well as enabling the compare outputs (co1e and co2e), selecting input edge sensitivity (iedg1 and iedg2) and levels of output polarity (olvl1 and olvl2). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer control 1 (tcr1) $002c ic1ie ic2ie oc1ie toie co1e iedg1 iedg2 olvl1 0000 0uu0 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer control 2 (tcr2) $002d 0 0 oc2ie 0 co2e 0 0 olvl2 0000 0000 tpg 50 05f4book page 4 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 6-5 16-bit programmable timer 6 ic1ie ?input capture 1 interrupt enable if this bit is set, a timer interrupt is enabled whenever the ic1f status ?g (in the timer status register) is set. 1 (set) interrupt enabled. 0 (clear) interrupt disabled. ic2ie ?input capture 2 interrupt enable if this bit is set, a timer interrupt is enabled whenever the ic2f status ?g (in the timer status register) is set. 1 (set) interrupt enabled. 0 (clear) interrupt disabled. oc1ie ?output compare 1 interrupt enable if this bit is set, a timer interrupt is enabled whenever the oc1f status ?g (in the timer status register) is set. 1 (set) interrupt enabled. 0 (clear) interrupt disabled. toie ?timer over?w interrupt enable if this bit is set, a timer interrupt is enabled whenever the tof status ?g (in the timer status register) is set. 1 (set) interrupt enabled. 0 (clear) interrupt disabled. co1e ?timer compare 1 output enable if this bit is set, the output from timer output compare 1 is enabled. 1 (set) output compare 1 enabled. 0 (clear) output compare 1 disabled. iedg1 ?input edge 1 when iedg1 is set, a positive-going edge on the tcap1 pin will trigger a transfer of the free-running counter value to the input capture register 1. when clear, a negative-going edge triggers the transfer. 1 (set) tcap1 is positive-going edge sensitive. 0 (clear) tcap1 is negative-going edge sensitive. tpg 51 05f4book page 5 tuesday, august 5, 1997 1:10 pm
motorola 6-6 MC68HC05F4 16-bit programmable timer 6 iedg2 ?input edge 2 when iedg2 is set, a positive-going edge on the tcap2 pin will trigger a transfer of the free-running counter value to the input capture register 2. when clear, a negative-going edge triggers the transfer. 1 (set) tcap2 is positive-going edge sensitive. 0 (clear) tcap2 is negative-going edge sensitive. olvl1 ?output level 1 when olv1 is set a high output level will be clocked into the output level register by the next successful output compare, and will appear on the tcmp1 pin. when clear, it will be a low level which will appear on the tcmp1 pin. 1 (set) a high output level will appear on the tcmp1 pin. 0 (clear) a low output level will appear on the tcmp1 pin. oc2ie ?output compare 2 interrupt enable if this bit is set, a timer interrupt is enabled whenever the oc2f status ?g (in the timer status register) is set. 1 (set) interrupt enabled. 0 (clear) interrupt disabled. co2e ?timer compare 2 output enable if this bit is set, the output from timer output compare 2 is enabled. 1 (set) output compare 2 enabled. 0 (clear) output compare 2 disabled. olvl2 ?output level 2 when olv2 is set a high output level will be clocked into the output level register by the next successful output compare, and will appear on the tcmp2 pin. when clear, it will be a low level which will appear on the tcmp2 pin. 1 (set) a high output level will appear on the tcmp2 pin. 0 (clear) a low output level will appear on the tcmp2 pin. tpg 52 05f4book page 6 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 6-7 16-bit programmable timer 6 6.2.2 timer status register (tsr) the timer status register ($002e) contains the status bits corresponding to the timer interrupt conditions ?ic1f, ic2f, oc1f, tof, tcap1, tcap2 and oc2f. accessing the timer status register satis?s the ?st condition required to clear the status bits. the remaining step is to access the register corresponding to the status bit. ic1f ?input capture 1 ?g this bit is set when the selected polarity of edge is detected by the input capture edge detector 1 at tcap1; an input capture interrupt will be generated, if ic1ie is set. ic1f is cleared by reading the tsr and then the input capture 1 low register ($0021). 1 (set) a valid input capture has occurred. 0 (clear) no input capture has occurred. ic2f ?input capture 2 ?g this bit is set when the selected polarity of edge is detected by the input capture edge detector 2 at tcap2; an input capture interrupt will be generated if ic2ie is set. ic2f is cleared by reading the tsr and then the input capture 2 low register ($0025). 1 (set) a valid input capture has occurred. 0 (clear) no input capture has occurred. oc1f ?output compare 1 ?g this bit is set when the output compare register 1 contents match those of the free-running counter; an output compare interrupt will be generated if oc1ie is set. oc1f is cleared by reading the tsr and then the output compare 1 low register ($0023). 1 (set) a valid output compare has occurred. 0 (clear) no output compare has occurred. tof ?timer over?w status ?g this bit is set when the free-running counter over?ws from $ffff to $0000; a timer over?w interrupt will occur if toie is set. tof is cleared by reading the tsr and the counter low register ($0029). 1 (set) timer over?w has occurred. 0 (clear) no timer over?w has occurred. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer status (tsr) $002e ic1f ic2f oc1f tof tcap1 tcap2 oc2f 0 uuuu uuu0 tpg 53 05f4book page 7 tuesday, august 5, 1997 1:10 pm
motorola 6-8 MC68HC05F4 16-bit programmable timer 6 when using the timer over?w function and reading the free-running counter at random times to measure an elapsed time, a problem may occur whereby the timer over?w ?g is unintentionally cleared if: 1 the timer status register is read or written when tof is set, and 2 the lsb of the free-running counter is read, but not for the purpose of servicing the ?g. reading the alternate counter register instead of the counter register will avoid this potential problem. tcap1 ?timer capture 1 ?g this bit re?cts the current state of the timer capture 1 input. tcap2 ?timer capture 2 ?g this bit re?cts the current state of the timer capture 2 input. oc2f ?output compare 2 ?g this bit is set when the output compare register 2 contents match those of the free-running counter; an output compare interrupt will be generated if oc2ie is set. oc2f is cleared by reading the tsr and then the output compare 2 low register ($0027). 1 (set) a valid output compare has occurred. 0 (clear) no output compare has occurred. tpg 54 05f4book page 8 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 6-9 16-bit programmable timer 6 6.3 input capture ?nput capture is a technique whereby an external signal is used to trigger a read of the free running counter. in this way it is possible to relate the timing of an external signal to the internal counter value, and hence to elapsed time. there are two input capture registers: input capture register 1 (icr1) and input capture register 2 (icr2). there are two input capture interrupt enable bits (ic1ie and ic2ie). 6.3.1 input capture register 1 (icr1) the two 8-bit registers that make up the 16-bit input capture register 1 are read-only, and are used to latch the value of the free-running counter after the input capture edge detector circuit 1 senses a valid transition at tcap1. the level transition that triggers the counter transfer is de?ed by the input edge bit (iedg1). when an input capture 1 occurs, the corresponding ?g ic1f in tsr is set. an interrupt can also accompany an input capture 1 provided the ic1ie bit in tcr1 is set. the 8 most signi?ant bits are stored in the input capture register 1 high at $0020, the 8 least signi?ant bits in the input capture register 1 low at $0021. the result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter, which is four internal bus clock cycles. the free-running counter contents are transferred to the input capture register 1 on each valid signal transition whether the input capture 1 ?g (ic1f) is set or clear. the input capture register 1 always contains the free-running counter value that corresponds to the most recent input capture 1. after a read of the input capture register 1 msb ($0020), the counter transfer is inhibited until the lsb ($0021) is also read. this characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. a read of the input capture register 1 lsb ($0021) does not inhibit the free-running counter transfer since the two actions occur on opposite edges of the internal bus clock. reset does not affect the contents of the input capture register 1, except when exiting stop mode (see section 6.5 ). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset input capture 1 high (icr1h) $0020 undetned input capture 1 low (icr1l) $0021 undetned tpg 55 05f4book page 9 tuesday, august 5, 1997 1:10 pm
motorola 6-10 MC68HC05F4 16-bit programmable timer 6 6.3.2 input capture register 2 (icr2) the two 8-bit registers that make up the 16-bit input capture register 2 are read-only, and are used to latch the value of the free-running counter after the input capture edge detector circuit 2 senses a valid transition at pin tcap2. when an input capture 2 occurs, the corresponding ?g ic2f in tsr is set. an interrupt can also accompany an input capture 2 provided the ic2ie bit in tcr1 is set. the 8 most signi?ant bits are stored in the input capture 2 high register at $0024, the 8 least signi?ant bits in the input capture 2 low register at $0025. the result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter, which is four internal bus clock cycles. the free-running counter contents are transferred to the input capture register 2 on each valid signal transition whether the input capture 2 ?g (ic2f) is set or clear. the input capture register 2 always contains the free-running counter value that corresponds to the most recent input capture 2. after a read of the input capture register 2 msb ($0024), the counter transfer is inhibited until the lsb ($0025) is also read. this characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. a read of the input capture register 2 lsb ($0024) does not inhibit the free-running counter transfer since the two actions occur on opposite edges of the internal bus clock. reset does not affect the contents of the input capture register 2, except when exiting stop mode (see section 6.5 ). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset input capture 2 high (icr2h) $0024 undetned input capture 2 low (icr2h) $0025 undetned tpg 56 05f4book page 10 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 6-11 16-bit programmable timer 6 6.4 output compare ?utput compare is a technique which may be used, for example, to generate an output waveform, or to signal when a speci? time period has elapsed, by presetting the output compare register to the appropriate value. there are two output compare registers: output compare register 1 (ocr1) and output compare register 2 (ocr2). there are two output compare interrupt enable bits (oc1ie and oc2ie). 6.4.1 output compare register 1 (ocr1) the 16-bit output compare register 1 is made up of two 8-bit registers at locations $0022 (msb) and $0023 (lsb). the contents of the output compare register 1 are compared with the contents of the free-running counter continually and, if a match is found, the corresponding output compare ?g (oc1f) in the timer status register is set. if the timer compare output enable bit (co1e) is set, the output level (olvl1) is transferred to pin tcmp1. the output compare register 1 values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. an interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (oc1ie) is set. (the free-running counter is updated every four internal bus clock cycles.) after a processor write cycle to the output compare register 1 containing the msb ($0022), the output compare function is inhibited until the lsb ($0023) is also written. the user must write both bytes (locations) if the msb is written ?st. a write made only to the lsb ($0023) will not inhibit the compare 1 function. the processor can write to either byte of the output compare register 1 without affecting the other byte. if the timer compare output enable bit (co1e) is set, the output level (olvl1) bit is clocked to the output level register and hence to the tcmp1 pin whether the output compare ?g 1 (oc1f) is set or clear. the minimum time required to update the output compare register 1 is a function of the program rather than the internal hardware. because the output compare ?g 1 and the output compare register 1 are not de?ed at power on, and not affected by reset, care must be taken when initializing output compare functions with software. the following procedure is recommended: write to output compare 1 high to inhibit further compares; read the timer status register to clear oc1f (if set); write to output compare 1 low to enable the output compare 1 function. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset output compare 1 high (ocr1h) $0022 undetned output compare 1 low (ocr1l) $0023 undetned tpg 57 05f4book page 11 tuesday, august 5, 1997 1:10 pm
motorola 6-12 MC68HC05F4 16-bit programmable timer 6 the purpose of this procedure is to prevent the oc1f bit from being set between the time it is read and the write to the corresponding output compare register. all bits of the output compare register are readable and writable and are not altered by the timer hardware or reset. if the compare function is not needed, the two bytes of the output compare register can be used as storage locations. 6.4.2 output compare register 2 (ocr2) the 16-bit output compare register 2 is made up of two 8-bit registers at locations $0026 (msb) and $0027 (lsb). the contents of the output compare register 2 are compared with the contents of the free-running counter continually and, if a match is found, the corresponding output compare ?g (oc2f) in the timer status register is set. if the timer compare 2 output enable bit (co2e) is set, the output level (olvl2) is transferred to pin tcmp2. the output compare register 2 values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. an interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (oc2ie) is set. (the free-running counter is updated every four internal bus clock cycles.) after a processor write cycle to the output compare register 2 containing the msb ($0026), the output compare function is inhibited until the lsb ($0027) is also written. the user must write both bytes (locations) if the msb is written ?st. a write made only to the lsb ($0027) will not inhibit the compare 2 function. the processor can write to either byte of the output compare register 2 without affecting the other byte. if the timer compare output enable bit (co2e) is set, the output level (olvl2) bit is clocked to the output level register and hence to the tcmp2 pin whether the output compare 2 ?g (oc2f) is set or clear. the minimum time required to update the output compare register 2 is a function of the program rather than the internal hardware. because the output compare 2 ?g and the output compare register 2 are not de?ed at power on, and not affected by reset, care must be taken when initializing output compare functions with software. the following procedure is recommended: write to output compare 2 high to inhibit further compares; read the timer status register to clear oc2f (if set); write to output compare 2 low to enable the output compare 2 function. the purpose of this procedure is to prevent the oc2f bit from being set between the time it is read and the write to the corresponding output compare register. all bits of the output compare register are readable and writable and are not altered by the timer hardware or reset. if the compare function is not needed, the two bytes of the output compare register can be used as storage locations. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset output compare 2 high (ocr2h) $0026 undetned output compare 2 low (ocr2h) $0027 undetned tpg 58 05f4book page 12 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 6-13 16-bit programmable timer 6 6.5 timer during stop mode when the mcu enters stop mode, the timer counter stops counting and remains at that particular count value until stop mode is exited by an interrupt. if stop mode is exited by power-on or external reset, the counter is forced to $fffc but if it is exited by an interrupt then the counter resumes from its stopped value. another feature of the programmable timer is that if at least one valid input capture edge occurs at one of the tcap pins while in stop mode, the corresponding input capture detect circuitry is armed. this action does not wake the mcu or set any timer ?gs, but when the mcu does wake-up there will be an active input capture ?g (and data) from that ?st valid edge which occurred during stop mode. if stop mode is exited by an external reset then no such input capture ?g or data action takes place even if there was a valid input capture edge (at one of the tcap pins) during stop mode. 6.6 timer during wait mode the cpu clock halts during wait mode, but the timer keeps running. if a reset is used to exit wait mode the counters are forced to $fffc. if interrupts are enabled, a timer interrupt will cause the processor to exit wait mode. 6.7 timer state diagrams the relationships between the internal clock signals, the counter contents and the status of the ?g bits are shown in figure 6-2 to figure 6-5 . it should be noted that the signals labelled ?nternal (processor clock, timer clocks and reset) are not available to the user. tpg 59 05f4book page 13 tuesday, august 5, 1997 1:10 pm
motorola 6-14 MC68HC05F4 16-bit programmable timer 6 figure 6-2 timer state timing diagram for reset figure 6-3 timer state timing diagram for input capture internal processor clock internal reset 16-bit counter external reset or end of por internal timer clocks ? ? ? $fffc $fffd $fffe $ffff note: the counter and timer control registers are the only ones affected by power-on or external reset. t00 t01 t11 t10 internal processor clock 16-bit counter $f123 $f124 $f125 $f126 internal timer clocks ? ? ? t00 t01 t11 t10 internal capture latch $f124 $???? input capture register input capture ?ag input edge } } } } note: if the input edge occurs in the shaded area from one timer state t10 to the next timer state t10, then the input capture ?ag will be set during the next t11 state. tpg 60 05f4book page 14 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 6-15 16-bit programmable timer 6 figure 6-4 timer state timing diagram for output compare figure 6-5 timer state timing diagram for timer over?w internal processor clock 16-bit counter $f456 $f457 $f458 $f459 internal timer clocks ? ? ? t00 t01 t11 t10 $f457 cpu writes $f457 output compare ?ag and tcmp1,2 note: 1 the cpu write to the compare registers may take place at any time, but a compare only occurs at timer state t01. thus a four cycle difference may exist between the write to the compare register and the actual compare. 2 the output compare ?ag is set at the timer state t11 that follows the comparison match ($f457 in this example). output compare register compare register latch (note 2) (note 1) (note 1) internal processor clock 16-bit counter $ffff $0000 $0001 $0002 internal timer clocks ? ? ? t00 t01 t11 t10 note: the timer over?ow ?ag is set at timer state t11 (transition of counter from $ffff to $0000). it is cleared by a read of the timer status register during the internal processor clock high time, followed by a read of the counter low register. timer over?ow ?ag tpg 61 05f4book page 15 tuesday, august 5, 1997 1:10 pm
motorola 6-16 MC68HC05F4 16-bit programmable timer this page left blank intentionally 6 tpg 62 05f4book page 16 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 7-1 dtmf/melody generator 7 7 dtmf/melody generator 7.1 introduction the dtmf/melody generator (dmg) is a multi-functional tone generator built into the MC68HC05F4 mcu which supports dtmf dialling, melody-on-hold and paci?r tone functions. 7.1.1 features 4 row and 4 column frequencies for dtmf dialling 24 row and 24 column frequencies for dual tone melody 28 frequencies for paci?r tone to acknowledge button pressed for pulse dialling power saving mechanism for output disable condition 3.579mhz/2 operation 6-bit d/a converter and 28 time steps for sine wave generation sine wave or square wave selectable output for melody (or dtmf) single or dual tone capability for melody (or dtmf) tpg 63 05f4book page 1 tuesday, august 5, 1997 1:10 pm
motorola 7-2 MC68HC05F4 dtmf/melody generator 7 7.2 functional description as shown in figure 7-1 , the dmg consists of 2 tone generation paths (the column and row paths). one path generates the row tone and the other the column tone, whose frequencies are determined by the values in the frequency control registers fcr and fcc respectively. the tones allowed at the tno output are single/dual sine/square wave tones of dtmf and melody frequencies, whereas at the tnx output, only single square wave tones are allowed. the method of tone generation for the two paths is almost the same, and is described as follows. to generate a sine wave tone with programmable frequency in a path, the internal clock (i.e. the 3.58mhz/2) is ?st divided by a frequency divider according to a number on the register (fcr or fcc). the output of the divider is a periodic pulse train whose frequency is the sampling rate of the desired ?taircase sine wave? this pulse train, in turn, clocks a divide-by-28 binary counter (pla scanner) whose 28 decoded outputs scan sequentially 28 memory locations of a 28x6 sine wave generator (pla) in 28 time steps (m). the six resulting digital sine wave bits are then fed separately to a 6-bit resistor ladder to produce a current signal. the method for generating a square wave tone in a path is similar to that of a sine wave tone except that only the most signi?ant bit of a sine wave pla is fed to the 6-bit resistor ladder to produce a current signal (the other 5 least signi?ant bits are masked by the sine/square wave select). using this method, a square wave tone can be produced which has exactly the same frequency and phase as a sine wave tone, and uses the same frequency control register value. after obtaining the current signals from the row and column paths, the row current signal is ?st attenuated by 2db. it is then summed with the column current signal, and is ?ally fed to an active 7 khz low pass ?ter to reduce harmonic distortion (note that square wave tones are also passed through this ?ter). the resulting dtmf or melody signal is output through the tno pin which is normally connected to a speech circuit. the generator provides not only dtmf and melody but also a square wave paci?r tone (tonex). this signal is also extracted from the most signi?ant bit of the sine wave pla of the row path, but is not passed through the ?ter. the tonex signal is output through the tnx pin which is normally connected to a loudspeaker. tpg 64 05f4book page 2 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 7-3 dtmf/melody generator 7 figure 7-1 dtmf/melody generator (dmg) block diagram row frequency divider pla scanner sine wave pla 28 x 6 bit sine/square wave select 6-bit resistor ladder mux row frequency divider pla scanner sine wave pla 28 x 6 bit sine/square wave select 6-bit resistor ladder high group pre-emphasis tnoe fcr register fcc register data validator stop ms1 ms0 tger tgec tno tristate control + msb lsb tnx 5 5 6 6 6 current summer active low pass ?ter + 3.58 mhz/2 tpg 65 05f4book page 3 tuesday, august 5, 1997 1:10 pm
motorola 7-4 MC68HC05F4 dtmf/melody generator 7 7.3 dmg registers the dmg has two registers (row frequency control register and column frequency control register) for row and column frequency selection respectively, and one register (tone control register) for tone output control and mode selection. 7.3.1 row and column frequency control registers fcr4?cr0 and fcc4?cc0 control the frequency of the tone signals on the row and the column paths respectively. the row and column paths are not exactly identical owing to the presence of the high group pre-emphasis in the column path. in order to avoid the entry of the row dtmf tone values to the column, and vice versa, the above cases are treated as illegal. the data validator will disable all outputs when an illegal value is detected. the bit description for dtmf and melody tone generation are shown in table 7-1 and table 7-2 respectively. it is the users responsibility to ensure good programming practice by initialising all registers to contain legal values for the desired function. 7.3.2 tone control register (tncr) this register controls the internal con?uration and tone output timing of the dtmf/melody generator. ms1, ms0 ?melody select for operation the ms0 and ms1 bits control the mode of operation of the dtmf/melody generator. there are sine wave, square wave 1, square wave 2 and square wave 3 modes. they are speci?d as shown in table 7-3 . when square wave 2 or square wave 3 mode is selected, the tnx pin is activated. the idle state for tnx is a logic high. the ?al state of the tnx pin is still dependant on the values of tger, tgec (see table 7-4 ), fcr and fcc bits (when illegal values are input). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset row freq. control (fcr) $000d 0 0 0 fcr4 fcr3 fcr2 fcr1 fcr0 undetned address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset column freq. control (fcc) $000e 0 0 0 fcc4 fcc3 fcc2 fcc1 fcc0 undetned address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset tone control (tncr) $000f ms1 ms0 tger tgec tnoe 0 0 0 0000 0000 tpg 66 05f4book page 4 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 7-5 dtmf/melody generator 7 the state of the tno pin depends on the value of the tnoe bit. after a reset, the tnoe is cleared and the tno pin is tristate. when tnoe is set, the tno output is activated. if the tger and tgec bits are held low and tnoe is set, the dc offset of v dd /2 appears at tno pin. in stop mode, the tnx pin is high and the tno pin is tristate. when both ms1 and ms0 are set (square wave 3), the generator can generate both single tone melody at the column path, and tonex at the row path simultaneously. tger ?tone generator enable row path 1 (set) row path on 0 (clear) row path off tgec ?tone generator enable column path 1 (set) column path on 0 (clear) column path off tnoe ?tone output enable 1 (set) tno on 0 (clear) tno off . table 7-1 bit description for dtmf generation fcr register fcc register tone standard frequency (hz) tone output frequency (hz) frequency deviation $00 f r1 697.0 694.8 e0.32 $01 f r2 770.0 770.1 0.02 $02 f r3 852.0 854.2 0.03 $03 f r4 941.0 940.0 e0.11 $10 f c1 1209.0 1206.0 e0.244 $11 f c2 1336.0 1331.7 e0.324 $12 f c3 1477.0 1486.5 0.645 $13 f c4 1633.0 1639.0 0.367 note: the legal values in the fcr register column are illegal to the fcc register, and vice versa. an input of illegal values to these registers will produce a high at tnx output and v dd /2 at tno output (tnoe = 1) tpg 67 05f4book page 5 tuesday, august 5, 1997 1:10 pm
motorola 7-6 MC68HC05F4 dtmf/melody generator 7 table 7-2 bit description for melody generator fcr/fcc register tone standard frequency (hz) tone output frequency (hz) frequency deviation (%) $04 d#5 622.3 620.6 e0.28 $05 e5 659.3 659.0 e0.05 $06 f5 698.5 694.8 e0.53 $07 f#5 740.0 743.3 0.44 $08 g5 784.0 779.5 e0.57 $09 g#5 830.6 830.1 e0.06 $0a a5 880.0 875.6 e0.50 $0b a#5 932.0 926.4 e0.64 $0c b5 987.8 983.4 e0.45 $0d c6 1046.5 1047.9 0.13 $0e c#6 1108.7 1102.1 e0.60 $0f d6 1174.7 1183.7 0.77 $14 d#6 1244.5 1253.3 0.71 $15 e6 1318.5 1331.7 1.00 $16 f6 1396.9 1389.6 e0.52 $17 f#6 1480.0 1486.5 0.44 $18 g6 1568.0 1559.0 e0.57 $19 g#6 1661.2 1682.1 1.26 $1a a6 1760.0 1775.6 0.89 $1b a#6 1864.7 1880.0 0.82 $1c b6 1975.5 1997.5 1.11 $1d c7 2093.0 2062.0 e1.49 $1e c#7 2217.5 2204.2 e0.60 $1f d7 2349.3 2367.4 0.771 table 7-3 mode of operation for dmg ms1 ms0 mode tnx output tno output 0 0 sine wave high sine wave row and column frequency 0 1 square wave 1 high square wave row and column frequency 1 0 square wave 2 row frequency square wave row and column frequency 1 1 square wave 3 row frequency square wave column frequency tpg 68 05f4book page 6 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 7-7 dtmf/melody generator 7 tger, tgec ?tone generation enable for row and column paths when both bits are held low, the dmg is disabled by forcing the two frequency counters and the two pla scanning counters to their reset states. the dmg should then consume zero dynamic power, if the tnoe bit is also cleared. when a tge bit for a path is held high (provided that the value in the frequency control register for that path is legal), the generator is enabled. all the counters associated with that path are then run from their reset states. the reset state of a frequency counter de?es the time=0 state of the time step, whereas at their reset state, the pla scanning counters, scanning the memory location, contain the dc values of the staircase sine wave. in dtmf dialling, the row and column tone values are ?st entered to the fcr and fcc registers. the tger and tgec bits are then set or reset simultaneously to achieve dual tone multiple frequency. similarly, in melody generation, one path is chosen as the high part, and the other as the low part. the tger and tgec bits are then set and reset according to the rhythm required by the musical piece. one can exhibit only single tone melody by disabling either tger or tgec permanently. the dtmf column and row frequency tones can also be output separately for testing by enabling just the one path. 7.4 operation of the dmg the dmg is recommended to be operated using the following procedures: to operate melody generation, the choice of sine wave or square wave output mode is totally up to the users taste. the sine wave melody has a sound like a ?te, whereas the square wave melody possesses much richer harmonics. the required tones are selected through the fcr and fcc registers. the selected tone is output when the corresponding tger or tgec bit and tnoe bit are set. the fcr register should contain the value representing the tone output frequency and the fcc register should contain a value of $04 or greater to ensure the output is not blocked by the data validator. table 7-4 effect of tone generation on dmg tger tgec row path column path 0 0 off off 0 1 off active 1 0 active off 1 1 active active tpg 69 05f4book page 7 tuesday, august 5, 1997 1:10 pm
motorola 7-8 MC68HC05F4 dtmf/melody generator 7 7.5 dmg during wait mode the dmg is still active during the wait mode. 7.6 dmg during stop mode in stop mode the oscillator is stopped causing the dmg to cease function. tpg 70 05f4book page 8 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 8-1 resets and interrupts 8 8 resets and interrupts 8.1 resets the MC68HC05F4 can be reset in ?e ways: by the initial power-on reset function, by an active low input to the reset pin, by an on-chip low voltage reset, by an opcode fetch from an illegal address, and by a cop watchdog timer reset. any of these resets will cause the program to return to its starting address, speci?d by the contents of memory locations $3ffe and $3fff, and cause the interrupt mask of the ccr to be set. 8.1.1 power-on reset a power-on reset occurs when a positive transition is detected on vdd. the power-on reset function is strictly for power turn-on conditions and should not be used to detect drops in the power supply voltage. the power-on circuitry provides a stabilization delay (t porl ) from when the oscillator becomes active. if the external reset pin is low at the end of this delay then the processor remains in the reset state until reset goes high. 8.1.2 reset pin when the oscillator is running in a stable state, the mcu is reset when a logic zero is applied to the reset input for a minimum period of 1.5 machine cycles (t cyc ). this pin contains an internal schmitt trigger as part of its input to improve noise immunity. when the reset pin goes high, the mcu will resume operation on the following cycle. the reset pin is also an output device for the internal low voltage reset. tpg 71 05f4book page 1 tuesday, august 5, 1997 1:10 pm
motorola 8-2 MC68HC05F4 resets and interrupts 8 8.1.3 illegal address reset when an opcode fetch occurs from an address which is not part of the ram ($0040 ?$013f) or of the rom ($3000 ?$3fff) or eeprom ($0200 ?$02ff), the device is automatically reset. note: no rts or rti instruction should be placed at the end of a memory block since this could result in an illegal address reset. 8.1.4 computer operating properly (cop) reset the mcu contains a watchdog timer that automatically times out if not reset (cleared) within a speci? time by a program reset sequence. if the cop watchdog timer is allowed to timeout, an internal reset is generated to reset the mcu. because the internal reset signal is used, the mcu comes out of a cop reset in the same operating mode it was in when the cop timeout was generated. the cop function is a mask option, enabled or disabled during device manufacture. see section 1.2 . refer to section 5.3 for more information on the cop watchdog timer. 8.1.5 low voltage reset the mcu contains a low voltage detection circuit which drives the external reset. for a positive transition of supply voltage v dd , the low voltage reset occurs as long as v dd is below the v ron level. in this case the external reset pin is pulled down. if the supply voltage drops off above the v ron level, the reset is released. if the supply voltage falls off below the v roff level, the reset pin is pulled down. tpg 72 05f4book page 2 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 8-3 resets and interrupts 8 8.2 interrupts the mcu can be interrupted by six different sources, ?e maskable hardware interrupts and one nonmaskable software interrupt: external signal on the irq pin keyboard interrupt core timer interrupt 16-bit programmable timer interrupt low voltage interrupt (lvi) ?eeprom software interrupt instruction (swi) interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (i-bit) to prevent additional interrupts. the rti instruction (return from interrupt) causes the register contents to be recovered from the stack and normal processing to resume. while executing the rti instruction, the interrupt mask bit (i-bit) will be cleared providing the corresponding enable bit stored on the stack is zero, i.e. the interrupt is disabled. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. the current instruction is the one already fetched and being operated on. when the current instruction is complete, the processor checks all pending hardware interrupts. if interrupts are not masked (ccr i-bit clear) and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. figure 8-1 shows the interrupt processing ?w. note: power-on or external reset clears all interrupt enable bits thus preventing interrupts during the reset sequence. tpg 73 05f4book page 3 tuesday, august 5, 1997 1:10 pm
motorola 8-4 MC68HC05F4 resets and interrupts 8 8.2.1 interrupt priorities each potential interrupt source is assigned a priority which means that if more than one interrupt is pending at the same time, the processor will service the one with the highest priority ?st. for example, if both an external interrupt and a timer interrupt are pending after an instruction execution, the external interrupt is serviced ?st. 8.2.2 non-maskable software interrupt (swi) the software interrupt (swi) is an executable instruction and a nonmaskable interrupt: it is executed regardless of the state of the i-bit in the ccr. if the i-bit is zero (interrupts enabled), swi is executed after interrupts that were pending when the swi was fetched, but before interrupts generated after the swi was fetched. the swi interrupt service routine address is speci?d by the contents of memory locations $3ffc and $3ffd. 8.2.3 maskable hardware interrupts if the interrupt mask bit (i-bit) of the ccr is set, all maskable interrupts (internal and external) are masked. clearing the i-bit allows interrupt processing to occur. irq is software selectable as either edge or edge-and-level sensitive (bit 3 of the system option register). note: the internal interrupt latch is cleared in the ?st part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the i-bit is cleared. 8.2.3.1 real time and core timer (ctimer) interrupts there are two different core timer interrupt ?gs that cause a ctimer interrupt whenever an interrupt is enabled and its ?g becomes set, namely rtif and ctof. the interrupt ?gs and enable bits are located in the ctimer control and status register (ctcsr). these interrupts will vector to the same interrupt service routine, whose start address is contained in memory locations $3ff8 and $3ff9 (see section 5.2.1 and figure 5-1 ). to make use of the real time interrupt the rtie bit must ?st be set. the rtif bit will then be set after the speci?d number of counts. to make use of the core timer over?w interrupt, the ctofe bit must ?st be set. the ctof bit will then be set when the core timer counter register over?ws from $ff to $00. tpg 74 05f4book page 4 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 8-5 resets and interrupts 8 figure 8-1 interrupt ?wchart core timer or cpi interrupt ? irq /key external interrupt ? is i-bit set ? swi instruction ? rti instruction ? from reset execute instruction restore registers from stack: cc, a, x, pc set i-bit stack: pc, x, a, cc clear relevant interrupt request latch no no no no no ye s ye s ye s ye s ye s timer interrupt lvi interrupt no no ye s ? ? fetch next instruction load pc from: swi: irq /key: ctimer: timer: lvi: $3ffc, $3ffd $3ffa, $3ffb $3ff8, $3ff9 $3ff6, $3ff7 $3ff4, $3ff5 tpg 75 05f4book page 5 tuesday, august 5, 1997 1:10 pm
motorola 8-6 MC68HC05F4 resets and interrupts 8 8.2.3.2 programmable 16-bit timer interrupt there are ?e different timer interrupt ?gs that cause a timer interrupt whenever they are set and enabled. the timer interrupt enable bits are located in the timer control register (tcr) and the timer interrupt ?gs are located in the timer status register (tsr). both interrupts will vector to the same service routine, whose start address is contained in memory locations $3ff6 and $3ff7. 8.2.3.3 keyboard interrupt when con?ured as input pins, all eight port a lines provide a wired-or keyboard interrupt facility and will generate an interrupt, provided that the keyboard interrupt enable bit (kie) in the key control register (kcr) is set. the address of the interrupt service routine is speci?d by the contents of memory locations $3ffa and $3ffb. since this interrupt vector is shared with the irq external interrupt function the interrupt service routine should check kf to determine the interrupt source. kf should be cleared by software in the interrupt service routine. care must be taken to allow adequate time for switch debounce before clearing the ?g. 8.2.3.4 low voltage interrupt there is a low voltage interrupt ?g that causes an interrupt whenever it is set and enabled. the low voltage interrupt enable bit and the interrupt ?g are located in the system option register (sor) described below in section 8.2.3.5 . this interrupt will vector to the service routine, located at the address speci?d by the contents of memory locations $3ff4 and $3ff5. table 8-1 vector address for interrupts and reset register flag name interrupts cpu interrupt vector address ? ? reset reset $3ffee$3fff ? ? software interrupt swi $3ffce$3ffd ? ? external interrupt irq $3ffae$3ffb ctcsr ctof core timer over?ow ctimer $3ff8e$3ff9 ctcsr rtif real time interrupt ctimer $3ff8e$3ff9 tsr ic1f timer input capture1 timer $3ff6e$3ff7 tsr oc1f timer output compare1 timer $3ff6e$3ff7 tsr ic2f timer input capture2 timer $3ff6e$3ff7 tsr oc2f timer output compare2 timer $3ff6e$3ff7 tsr tof timer over?ow timer $3ff6e$3ff7 kcr kf keyboard interrupt keyf $3ffae$3ffb sor lvif low voltage interrupt lvi $3ff4e$3ff5 tpg 76 05f4book page 6 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 8-7 resets and interrupts 8 8.2.3.5 system options register the MC68HC05F4 mcu contains a system options register which is located at address $11. this register is used to control the lvi and the clock system. note: the lvi uses the voltage reference of the low voltage reset (lvr) circuitry. this means that the lvi can only be used if the lvr is enabled by mask option. lvif ?low voltage interrupt ?g 1 (set) a low voltage interrupt has occurred. 0 (clear) no low voltage interrupt has occurred. lvif is a read only status bit and is set by the low voltage detection circuit, if power supply vdd falls below v lvi , provided the lvr is enabled (mask option) and the lvion and lvie bits are set. the lvif ?g is reset by clearing the lvie bit. the lvi circuit is rearmed by again setting the lvie bit. lvie ?low voltage interrupt enable 1 (set) low voltage interrupt and ?g generation is enabled. 0 (clear) low voltage interrupt and ?g generation is disabled. setting this bit enables the low voltage ?g and interrupt generation. a cpu interrupt request will then be generated whenever the lvif bit becomes set and the l-bit in the ccr is clear. lvion ?low voltage interrupt on 1 (set) power is supplied to the lvi circuitry. 0 (clear) lvi circuitry is disconnected from the power supply. setting this bit applies power to the lvi circuitry. if the lvi function is not used this bit should be cleared to save power. note: this bit must be set at least one instruction cycle before setting the lvie bit, to give the lvi circuitry time to stabilize. for descriptions of bits sc and irq see section 2.3 . address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset system options register (sor) $0011 lvif lvie lvion sc irq 0 0 0 0000 0000 tpg 77 05f4book page 7 tuesday, august 5, 1997 1:10 pm
motorola 8-8 MC68HC05F4 resets and interrupts 8 8.2.4 hardware controlled interrupt sequence the following three functions (reset, stop, and wait) are not in the strictest sense interrupts. however, they are acted upon in a similar manner. flowcharts for stop and wait are shown in figure 2-1 . reset: a reset condition causes the program to vector to its starting address, which is contained in memory locations $3ffe (msb) and $3fff (lsb). the i-bit in the condition code register is also set, to disable interrupts. stop: the stop instruction causes the oscillator to be turned off and the processor to ?leep until an external interrupt (irq ), a low voltage interrupt (lvi) or a keyboard interrupt occurs, or the device is reset. wait: the wait instruction causes all processor clocks to stop, but leaves the timer clocks running. this ?est state of the processor can be cleared by reset, an external interrupt (irq ), a keyboard interrupt, a timer interrupt (core or 16-bit) or an lvi interrupt. there are no special wait vectors for these interrupts. tpg 78 05f4book page 8 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 9-1 cpu core and instruction set 9 9 cpu core and instruction set this section provides a description of the cpu core registers, the instruction set and the addressing modes of the MC68HC05F4. 9.1 registers the mcu contains ?e registers, as shown in the programming model of figure 9-1. the interrupt stacking order is shown in figure 9-2. 9.1.1 accumulator (a) the accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. figure 9-1 programming model accumulator index register program counter stack pointer condition code register carry / borrow zero negative interrupt mask half carry 70 70 15 7 0 0 15 7 0 0 0 0 0 0 0 0 1 1 70 1 1 1 h i n z c tpg 79 05f4book page 1 tuesday, august 5, 1997 1:10 pm
motorola 9-2 MC68HC05F4 cpu core and instruction set 9 9.1.2 index register (x) the index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. the index register may also be used as a temporary storage area. 9.1.3 program counter (pc) the program counter is a 16-bit register, which contains the address of the next byte to be fetched. 9.1.4 stack pointer (sp) the stack pointer is a 16-bit register, which contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the ten most signi?ant bits are permanently set to 0000000011. these ten bits are appended to the six least signi?ant register bits to produce an address within the range of $00c0 to $00ff. subroutines and interrupts may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses ?e locations. 9.1.5 condition code register (ccr) the ccr is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the ?th bit indicates whether interrupts are masked. these bits can be individually tested by a program, and speci? actions can be taken as a result of their state. each bit is explained in the following paragraphs. figure 9-2 stacking order condition code register accumulator index register program counter high program counter low 70 stack unstack decreasing memory address increasing memory address interrupt return tpg 80 05f4book page 2 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 9-3 cpu core and instruction set 9 half carry (h) this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. interrupt (i) when this bit is set, all maskable interrupts are masked. if an interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. negative (n) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. zero (z) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. carry/borrow (c) when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit is also affected during bit test and branch instructions and during shifts and rotates. 9.2 instruction set the mcu has a set of 62 basic instructions. they can be grouped into ?e different types as follows: register/memory read/modify/write branch bit manipulation control the following paragraphs brie? explain each type. all the instructions within a given type are presented in individual tables. this mcu uses all the instructions available in the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. this instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is then stored in the index register and the low-order product is stored in the accumulator. a detailed definition of the mul instruction is shown in table 9-1 . tpg 81 05f4book page 3 tuesday, august 5, 1997 1:10 pm
motorola 9-4 MC68HC05F4 cpu core and instruction set 9 9.2.1 register/memory instructions most of these instructions use two operands. the ?st operand is either the accumulator or the index register. the second operand is obtained from memory using one of the addressing modes. the jump unconditional (jmp) and jump to subroutine (jsr) instructions have no register operand. refer to table 9-2 for a complete list of register/memory instructions. 9.2.2 branch instructions these instructions cause the program to branch if a particular condition is met; otherwise, no operation is performed. branch instructions are two-byte instructions. refer to table 9-3 . 9.2.3 bit manipulation instructions the mcu can set or clear any writable bit that resides in the ?st 256 bytes of the memory space (page 0). all port data and data direction registers, timer and serial interface registers, control/status registers and a portion of the on-chip ram reside in page 0. an additional feature allows the software to test and branch on the state of any bit within these locations. the bit set, bit clear, bit test and branch functions are all implemented with single instructions. for the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. refer to table 9-4 . 9.2.4 read/modify/write instructions these instructions read a memory location or a register, modify or test its contents, and write the modi?d value back to memory or to the register. the test for negative or zero (tst) instruction is an exception to this sequence of reading, modifying and writing, since it does not modify the value. refer to table 9-5 for a complete list of read/modify/write instructions. 9.2.5 control instructions these instructions are register reference instructions and are used to control processor operation during program execution. refer to table 9-6 for a complete list of control instructions. tpg 82 05f4book page 4 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 9-5 cpu core and instruction set 9 9.2.6 tables tables for all the instruction types listed above follow. in addition there is a complete alphabetical listing of all the instructions (see table 9-7 ), and an opcode map for the instruction set of the m68hc05 mcu family (see table 9-8 ). 9.3 addressing modes ten different addressing modes provide programmers with the ?xibility to optimize their code for all situations. the various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the memory space. short indexed accesses are single byte instructions; the longest instructions (three bytes) enable access to tables throughout memory. short absolute (direct) and long absolute (extended) addressing are also included. one or two byte direct addressing instructions access all data bytes in most applications. extended addressing permits jump instructions to reach all memory locations. the term ?ffective address (ea) is used in describing the various addressing modes. the effective address is de?ed as the address from which the argument for an instruction is fetched or stored. the ten addressing modes of the processor are described below. parentheses are used to indicate ?ontents of the location or register referred to. for example, (pc) indicates the contents of the location pointed to by the pc (program counter). an arrow indicates ?s replaced by and a colon indicates concatenation of two bytes. for additional details and graphical illustrations, refer to the m6805 hmos/m146805 cmos family microcomputer/ microprocessor user's manual or to the m68hc05 applications guide . table 9-1 mul instruction operation x:a ? x*a description multiplies the eight bits in the index register by the eight bits in the accumulator and places the 16-bit result in the concatenated accumulator and index register. condition codes h : cleared i : not affected n : not affected z : not affected c : cleared source mul form addressing mode cycles bytes opcode inherent 11 1 $42 tpg 83 05f4book page 5 tuesday, august 5, 1997 1:10 pm
motorola 9-6 MC68HC05F4 cpu core and instruction set 9 9.3.1 inherent in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. operations specifying only the index register or accumulator, as well as the control instruction, with no other arguments are included in this mode. these instructions are one byte long. 9.3.2 immediate in the immediate addressing mode, the operand is contained in the byte immediately following the opcode. the immediate addressing mode is used to access constants that do not change during program execution (e.g. a constant used to initialize a loop counter). ea = pc+1; pc ? pc+2 table 9-2 register/memory instructions addressing modes immediate direct extended indexed (no offset) indexed (8-bit offset) indexed (16-bit offset) function mnemonic opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles load a from memory lda a6 2 2 b6 2 3 c6 3 4 f6 1 3 e6 2 4 d6 3 5 load x from memory ldx ae 2 2 be 2 3 ce 3 4 fe 1 3 ee 2 4 de 3 5 store a in memory sta b7 2 4 c7 3 5 f7 1 4 e7 2 5 d7 3 6 store x in memory stx bf 2 4 cf 3 5 ff 1 4 ef 2 5 df 3 6 add memory to a add ab 2 2 bb 2 3 cb 3 4 fb 1 3 eb 2 4 db 3 5 add memory and carry to a adc a9 2 2 b9 2 3 c9 3 4 f9 1 3 e9 2 4 d9 3 5 subtract memory sub a0 2 2 b0 2 3 c0 3 4 f0 1 3 e0 2 4 d0 3 5 subtract memory from a with borrow sbc a2 2 2 b2 2 3 c2 3 4 f2 1 3 e2 2 4 d2 3 5 and memory with a and a4 2 2 b4 2 3 c4 3 4 f4 1 3 e4 2 4 d4 3 5 or memory with a ora aa 2 2 ba 2 3 ca 3 4 fa 1 3 ea 2 4 da 3 5 exclusive or memory with a eor a8 2 2 b8 2 3 c8 3 4 f8 1 3 e8 2 4 d8 3 5 arithmetic compare a with memory cmp a1 2 2 b1 2 3 c1 3 4 f1 1 3 e1 2 4 d1 3 5 arithmetic compare x with memory cpx a3 2 2 b3 2 3 c3 3 4 f3 1 3 e3 2 4 d3 3 5 bit test memory with a (logical compare) bit a5 2 2 b5 2 3 c5 3 4 f5 1 3 e5 2 4 d5 3 5 jump unconditional jmp bc 2 2 cc 3 3 fc 1 2 ec 2 3 dc 3 4 jump to subroutine jsr bd 2 5 cd 3 6 fd 1 5 ed 2 6 dd 3 7 tpg 84 05f4book page 6 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 9-7 cpu core and instruction set 9 9.3.3 direct in the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. ea = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) table 9-3 branch instructions relative addressing mode function mnemonic opcode # bytes # cycles branch always bra 20 2 3 branch never brn 21 2 3 branch if higher bhi 22 2 3 branch if lower or same bls 23 2 3 branch if carry clear bcc 24 2 3 (branch if higher or same) (bhs) 24 2 3 branch if carry set bcs 25 2 3 (branch if lower) (blo) 25 2 3 branch if not equal bne 26 2 3 branch if equal beq 27 2 3 branch if half carry clear bhcc 28 2 3 branch if half carry set bhcs 29 2 3 branch if plus bpl 2a 2 3 branch if minus bmi 2b 2 3 branch if interrupt mask bit is clear bmc 2c 2 3 branch if interrupt mask bit is set bms 2d 2 3 branch if interrupt line is low bil 2e 2 3 branch if interrupt line is high bih 2f 2 3 branch to subroutine bsr ad 2 6 table 9-4 bit manipulation instructions addressing modes bit set/clear bit test and branch function mnemonic opcode # bytes # cycles opcode # bytes # cycles branch if bit n is set brset n (n=0e7) 2n 3 5 branch if bit n is clear brclr n (n=0e7) 01+2n 3 5 set bit n bset n (n=0e7) 10+2n 2 5 clear bit n bclr n (n=0e7) 11+2n 2 5 tpg 85 05f4book page 7 tuesday, august 5, 1997 1:10 pm
motorola 9-8 MC68HC05F4 cpu core and instruction set 9 table 9-5 read/modify/write instructions addressing modes inherent (a) inherent (x) direct indexed (no offset) indexed (8-bit offset) function mnemonic opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles increment inc 4c 1 3 5c 1 3 3c 2 5 7c 1 5 6c 2 6 decrement dec 4a 1 3 5a 1 3 3a 2 5 7a 1 5 6a 2 6 clear clr 4f 1 3 5f 1 3 3f 2 5 7f 1 5 6f 2 6 complement com 43 1 3 53 1 3 33 2 5 73 1 5 63 2 6 negate (two?s complement) neg 40 1 3 50 1 3 30 2 5 70 1 5 60 2 6 rotate left through carry rol 49 1 3 59 1 3 39 2 5 79 1 5 69 2 6 rotate right through carry ror 46 1 3 56 1 3 36 2 5 76 1 5 66 2 6 logical shift left lsl 48 1 3 58 1 3 38 2 5 78 1 5 68 2 6 logical shift right lsr 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6 arithmetic shift right asr 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6 test for negative or zero tst 4d 1 3 5d 1 3 3d 2 4 7d 1 4 6d 2 5 multiply mul 42 1 11 table 9-6 control instructions inherent addressing mode function mnemonic opcode # bytes # cycles transfer a to x tax 97 1 2 transfer x to a txa 9f 1 2 set carry bit sec 99 1 2 clear carry bit clc 98 1 2 set interrupt mask bit sei 9b 1 2 clear interrupt mask bit cli 9a 1 2 software interrupt swi 83 1 10 return from subroutine rts 81 1 6 return from interrupt rti 80 1 9 reset stack pointer rsp 9c 1 2 no-operation nop 9d 1 2 stop stop 8e 1 2 wait wait 8f 1 2 tpg 86 05f4book page 8 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 9-9 cpu core and instruction set 9 table 9-7 instruction set mnemonic addressing modes condition codes inh imm dir ext rel ix ix1 ix2 bsc btb h i n z c adc add and asl asr bcc bclr bcs beq bhcc bhcs bhi bhs bih bil bit blo bls bmc bmi bms bne bpl bra brn brclr brset bset bsr clc 0 cli 0 clr 01 cmp condition code symbols h half carry (from bit 3) tested and set if true, cleared otherwise i interrupt mask not affected n negate (sign bit) ? load ccr from stack z zero 0 cleared c carry/borrow 1 set not implemented address mode abbreviations bsc bit set/clear imm immediate btb bit test & branch ix indexed (no offset) dir direct ix1 indexed, 1 byte offset ext extended ix2 indexed, 2 byte offset inh inherent rel relative tpg 87 05f4book page 9 tuesday, august 5, 1997 1:10 pm
motorola 9-10 MC68HC05F4 cpu core and instruction set 9 com 1 cpx dec eor inc jmp jsr lda ldx lsl lsr 0 mul 00 neg nop ora rol ror rsp rti ????? rts sbc sec 1 sei 1 sta stop 0 stx sub swi 1 tax tst txa wait 0 table 9-7 instruction set (continued) mnemonic addressing modes condition codes inh imm dir ext rel ix ix1 ix2 bsc btb h i n z c condition code symbols h half carry (from bit 3) tested and set if true, cleared otherwise i interrupt mask not affected n negate (sign bit) ? load ccr from stack z zero 0 cleared c carry/borrow 1 set not implemented address mode abbreviations bsc bit set/clear imm immediate btb bit test & branch ix indexed (no offset) dir direct ix1 indexed, 1 byte offset ext extended ix2 indexed, 2 byte offset inh inherent rel relative tpg 88 05f4book page 10 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 9-11 cpu core and instruction set 9 table 9-8 m68hc05 opcode map bit manipulation branch read/modify/write control register/memory btb bsc rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix high 0123456789abcdef high low 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 low 0 0000 553533659 234543 0 0000 brset0 bset0 bra neg nega negx neg neg rti sub sub sub sub sub sub 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 1 0001 553 6 234543 1 0001 brclr0 bclr0 brn rts cmp cmp cmp cmp cmp cmp 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 2 0010 553 11 234543 2 0010 brset1 bset1 bhi mul sbc sbc sbc sbc sbc sbc 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 3 0011 5535336510 234543 3 0011 brclr1 bclr1 bls com coma comx com com swi cpx cpx cpx cpx cpx cpx 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 4 0100 55353365 234543 4 0100 brset2 bset2 bcc lsr lsra lsrx lsr lsr and and and and and and 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 0101 553 234543 5 0101 brclr2 bclr2 bcs bit bit bit bit bit bit 3 btb 2 bsc 2 rel 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 6 0110 55353365 234543 6 0110 brset3 bset3 bne ror rora rorx ror ror lda lda lda lda lda lda 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 7 0111 55353365 2 45654 7 0111 brclr3 bclr3 beq asr asra asrx asr asr tax sta sta sta sta sta 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix 8 1000 55353365 2234543 8 1000 brset4 bset4 bhcc lsl lsla lslx lsl lsl clc eor eor eor eor eor eor 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 9 1001 55353365 2234543 9 1001 brclr4 bclr4 bhcs rol rola rolx rol rol sec adc adc adc adc adc adc 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix a 1010 55353365 2234543 a 1010 brset5 bset5 bpl dec deca decx dec dec cli ora ora ora ora ora ora 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix b 1011 553 2234543 b 1011 brclr5 bclr5 bmi sei add add add add add add 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix c 1100 55353365 2 23432 c 1100 brset6 bset6 bmc inc inca incx inc inc rsp jmp jmp jmp jmp jmp 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix d 1101 55343354 2656765 d 1101 brclr6 bclr6 bms tst tsta tstx tst tst nop bsr jsr jsr jsr jsr jsr 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 rel 2 dir 3 ext 3 ix2 2 ix1 1 ix e 1110 553 2 234543 e 1110 brset7 bset7 bil stop ldx ldx ldx ldx ldx ldx 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix f 1111 5535336522 45654 f 1111 brclr7 bclr7 bih clr clra clrx clr clr wait txa stx stx stx stx stx 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix f 1111 3 0 0000 sub 1ix opcode in hexadecimal opcode in binary address mode cycles bytes mnemonic legend abbreviations for address modes and registers bsc btb dir ext inh imm ix ix1 ix2 rel a x bit set/clear bit test and branch direct extended inherent immediate indexed (no offset) indexed, 1 byte (8-bit) offset indexed, 2 byte (16-bit) offset relative accumulator index register not implemented tpg 89 05f4book page 11 tuesday, august 5, 1997 1:10 pm
motorola 9-12 MC68HC05F4 cpu core and instruction set 9 9.3.4 extended in the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. when using the motorola assembler, the user need not specify whether an instruction uses direct or extended addressing. the assembler automatically selects the short form of the instruction. ea = (pc+1):(pc+2); pc ? pc+3 address bus high ? (pc+1); address bus low ? (pc+2) 9.3.5 indexed, no offset in the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. this addressing mode can access the ?st 256 memory locations. these instructions are only one byte long. this mode is often used to move a pointer through a table or to hold the address of a frequently referenced ram or i/o location. ea = x; pc ? pc+1 address bus high ? 0; address bus low ? x 9.3.6 indexed, 8-bit offset in the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. therefore the operand can be located anywhere within the lowest 511 memory locations. this addressing mode is useful for selecting the mth element in an n element table. ea = x+(pc+1); pc ? pc+2 address bus high ? k; address bus low ? x+(pc+1) where k = the carry from the addition of x and (pc+1) 9.3.7 indexed, 16-bit offset in the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. this address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. ea = x+[(pc+1):(pc+2)]; pc ? pc+3 address bus high ? (pc+1)+k; address bus low ? x+(pc+2) where k = the carry from the addition of x and (pc+2) tpg 90 05f4book page 12 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 9-13 cpu core and instruction set 9 9.3.8 relative the relative addressing mode is only used in branch instructions. in relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the pc if, and only if, the branch conditions are true. otherwise, control proceeds to the next instruction. the span of relative addressing is from ?26 to +129 from the opcode address. the programmer need not calculate the offset when using the motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. ea = pc+2+(pc+1); pc ? ea if branch taken; otherwise ea = pc ? pc+2 9.3.9 bit set/clear in the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. the byte following the opcode speci?s the address of the byte in which the speci?d bit is to be set or cleared. any read/write bit in the ?st 256 locations of memory, including i/o, can be selectively set or cleared with a single two-byte instruction. ea = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) 9.3.10 bit test and branch the bit test and branch addressing mode is a combination of direct addressing and relative addressing. the bit to be tested and its condition (set or clear) is included in the opcode. the address of the byte to be tested is in the single byte immediately following the opcode byte (ea1). the signed relative 8-bit offset in the third byte (ea2) is added to the pc if the speci?d bit is set or cleared in the speci?d memory location. this single three-byte instruction allows the program to branch based on the condition of any readable bit in the ?st 256 locations of memory. the span of branch is from ?25 to +130 from the opcode address. the state of the tested bit is also transferred to the carry bit of the condition code register. ea1 = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) ea2 = pc+3+(pc+2); pc ? ea2 if branch taken; otherwise pc ? pc+3 tpg 91 05f4book page 13 tuesday, august 5, 1997 1:10 pm
motorola 9-14 MC68HC05F4 cpu core and instruction set this page left blank intentionally 9 tpg 92 05f4book page 14 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 10-1 electrical specifications 10 10 electrical specifications this section contains the electrical speci?ations and associated timing information for the MC68HC05F4. 10.1 maximum ratings note: this device contains circuitry designed to protect against damage due to high electrostatic voltages or electric ?lds. however, it is recommended that normal precautions be taken to avoid the application of any voltages higher than those given in the maximum ratings table to this high impedance circuit. for maximum reliability all unused inputs should be tied to either v ss or v dd . (1) all voltages are with respect to v ss . (2) maximum current drain per pin is for one pin at a time, limited by an external resistor. table 10-1 maximum ratings rating (1) symbol value unit supply voltage v dd e 0.3 to + 0.7 v input voltage v in v ss e 0.3 to v ss + 0.3 v bootloader mode (irq pin only) v in v ss e 0.3 to 2 x v dd + 0.3 v current drain per pin (2) ? excluding vdd and vss i25ma operating temperature range ? standard ? extended t t l to t h 0 to + 70 e 40 to + 85 c storage temperature range t stg e 65 to + 150 c tpg 93 05f4book page 1 tuesday, august 5, 1997 1:10 pm
motorola 10-2 MC68HC05F4 electrical specifications 10 10.2 thermal characteristics and power considerations the average chip junction temperature, t j , in degrees celsius can be obtained from the following equation: where: t a = ambient temperature ( c) q ja = package thermal resistance, junction-to-ambient ( c/w) p d = p int + p i/o (w) p int = internal chip power = i dd ?v dd (w) p i/o = power dissipation on input and output pins (user determined) an approximate relationship between p d and t j (if p i/o is neglected) is: solving equations [1] and [2] for k gives: where k is a constant for a particular part. k can be determined by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained for any value of t a by solving the above equations. the package thermal characteristics are shown in table 10-2 . table 10-2 package thermal characteristics characteristics symbol value unit thermal resistance ? 44-pin qfp package ? 28-pin soic package ? 28 pin pdip package q ja 60 c/w t j t a p d q ja () + = p d k t j 273 + ---------------------- = kp d t a 273 + () q ja p d 2 + = tpg 94 05f4book page 2 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 10-3 electrical specifications 10 10.3 dc electrical characteristics (1) typical values are at midpoint of voltage range and at 25 c only. (2) all i dd measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in cmos designs. run and wait i dd : measured using an external square-wave clock source (f osc = 3.58 mhz); all inputs0.2v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). wait i dd : only the timer system and dmg active; current varies linearly with the osc2 capacitance. stop and wait i dd : all ports contgured as inputs, v il = 0.2 v, v ih = v dd e 0.2 v. stop i dd : measured with osc1 = v ss . table 10-3 dc electrical characteristics (v dd = 5.0 v) (v dd = 5.0v dc 10%, v ss = 0 v dc , t = e 40 c to 85 c, unless otherwise stated ) characteristic symbol min. typ. (1) max. unit output voltage i load = e10 m a i load = +10 m a v oh v ol v dd e 0.1 ? ? ? ? 0.1 v v output high voltage (i load = e0.8 ma) ports (pa0e7, pb2e7, pc0e7) v oh v dd e 0.8 ? ? v output low voltage (i load = +1.6 ma) ports(pa0e7, pb0e7, pc0e7, pd0e7) tcmp1e2 v ol ? ? 0.4 v input high voltage ports (pa0e7, pb0e7, pc0e7, pd0e7) irq , reset ,osc1, tcap1e2 v ih 0.7v dd ?v dd v input low voltage ports (pa0e7, pb0e7, pc0e7, pd0e7) irq , reset , osc1, tcap1e2 v il v ss ? 0.2v dd v supply current (2) run wait stop i dd ? ? ? 2.5 0.8 ? 5 1.2 80 ma ma m a i/o ports hi-z leakage current ports (pa0e7, pb0e7, pc0e7, pd0e7) i oz ??10 m a input current reset , irq , osc1, tcap1e2 i in ??1 m a capacitance ports (as input or output) reset , irq c out c in ? ? ? ? 12 8 pf pf input current low, v in = 0v ports (pa0e7, pb2e3, pc0e7), reset input current high, v in = v dd pb4e7 i il i ih e 30 30 e 90 90 e 170 170 m a m a tpg 95 05f4book page 3 tuesday, august 5, 1997 1:10 pm
motorola 10-4 MC68HC05F4 electrical specifications 10 caution: there is a restriction on the use of indexed addressing for eeprom read operations. when the base address of an indexed read of an eeprom location is within the eeprom address range ($0400 to $04ff), the read may not be successful. e.g. lda (base address), x ?may not give the correct result when the base address is in the range $0400 to $04ff. however, if the base address is outwith the eeprom address range, the read operation will be successful. this restriction applies to all operations capable of using indexed addressing. (1) typical values are at midpoint of voltage range and at 25 c only. (2) all i dd measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in cmos designs. run and wait i dd : measured using an external square-wave clock source (f osc = 3.58 mhz); all inputs0.2v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). wait i dd : only the timer system and dmg active; current varies linearly with the osc2 capacitance. stop and wait i dd : all ports contgured as inputs, v il = 0.2 v, v ih = v dd e 0.2 v. stop i dd : measured with osc1 = v ss . table 10-4 dc electrical characteristics (v dd = 2.7 v) (v dd = 2.7 v dc min, v ss = 0 v dc , t = e 40 c to 85 c, unless otherwise stated ) characteristic symbol min. typ. (1) max. unit output voltage i load = e10 m a i load = +10 m a v oh v ol v dd e 0.1 ? ? ? ? 0.1 v v output high voltage (i load = e0.2 ma) ports (pa0e7, pb2e7, pc0e7) v oh v dd e 0.3 ? ? v output low voltage (i load = + 0.4 ma) ports(pa0e7, pb0e7, pc0e7, pd0e7) tcmp1e2 v ol ? ? 0.3 v input high voltage ports (pa0e7, pb0e7, pc0e7, pd0e7) irq , reset ,osc1, tcap1e2 v ih 0.7v dd ?v dd v input low voltage ports (pa0e7, pb0e7, pc0e7, pd0e7) irq , reset , osc1, tcap1e2 v il v ss ? 0.2v dd v supply current (2) run wait stop i dd ? ? ? 1.5 0.5 ? 3.0 1.0 40 ma ma m a i/o ports hi-z leakage current ports (pa0e7, pb0e7, pc0e7, pd0e7) i oz ??10 m a input current reset , irq , osc1, tcap1e2 i in ??1 m a capacitance ports (as input or output) reset , irq c out c in ? ? ? ? 12 8 pf pf input current low, v in = 0v ports (pa0e7, pb2e3, pc0e7), reset input current high, v in = v dd pb4e7 i il i ih e 5 5 e 15 15 e 40 40 m a m a tpg 96 05f4book page 4 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 10-5 electrical specifications 10 10.4 control timing (1) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . table 10-5 control timing (v dd = 5v) (v dd = 5.0 v dc 10%, v ss = 0 v dc , t = t l to t h ) characteristic symbol min. max. unit frequency of operation: crystal external clock f osc ? dc 3.579 3.579 mhz internal operating frequency: crystal external clock f op ? dc 1.789 1.789 mhz processor cycle time t cyc 559.0 ? ns stop recovery start-up time t ilch ?20ms crystal oscillator start-up time t oxov ? 20.0 ms reset pulse width t rl 1.5 ? t cyc interrupt pulse width low (edge-triggered) t ilih 250.0 ? ns interrupt pulse period t ilil (1) ?t cyc osc1 pulse width t oh , t ol 100.0 ? ns eeprom byte programming time t epgm ? 15.0 ms eeprom byte erase time t ebyte ? 15.0 ms eeprom block erase time t eblock ? 100.0 ms eeprom bulk erase time t ebulk ? 300.0 ms eeprom programming voltage fall time t fpv ? 10.0 m s eeprom minimum programming voltage v ccmin 2.7 ? v tpg 97 05f4book page 5 tuesday, august 5, 1997 1:10 pm
motorola 10-6 MC68HC05F4 electrical specifications 10 (1) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . table 10-6 control timing (v dd = 2.7v) (v dd = 2.7 v dc min, v ss = 0 v dc , t = t l to t h ) characteristic symbol min. max. unit frequency of operation: crystal external clock f osc f osc ? dc 3.579 3.579 mhz mhz internal operating frequency: crystal external clock f op f op ? dc 1.789 1.789 mhz mhz processor cycle time t cyc 559.0 ? ns crystal oscillator start-up time t oxov ? 20.0 ms stop recovery start-up time t ilch ?20ms reset pulse width t rl 1.5 ? tcyc interrupt pulse width low (edge-triggered) t ilih 250.0 ? ns interrupt pulse period t ilil (1) ?t cyc osc1 pulse width toh, tol 100.0 ? ns eeprom byte programming time t epgm ? 15.0 ms eeprom byte erase time t ebyte ? 15.0 ms eeprom block erase time t eblock ? 100.0 ms eeprom bulk erase time t ebulk ? 300.0 ms eeprom programming voltage fall time t fpv ? 10.0 m s eeprom minimum programming voltage v ccmin 2.7 ? v tpg 98 05f4book page 6 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 10-7 electrical specifications 10 10.5 dc levels for low voltage reset and lvi 10.6 electrical speci?ations for dtmf/melody generator table 10-7 dc levels for low voltage reset and lvi (t = e 40 c to 85 c, unless otherwise stated) characteristic symbol min. typ. max. unit power-on reset voltage v ron 2.55 2.8 3.05 v power-off reset voltage v roff 2.45 2.7 2.95 v low voltage interrupt v lvi 2.75 3.0 3.25 v table 10-8 sine wave tones at tno characteristic min. typ. max. unit operating voltage 2.7 ? 5.5 v tone output level: low group e row high group e column 0.120 0.160 0.160 0.205 0.210 0.280 v rms v rms frequency deviation (dtmf) e 0.65 ? + 0.65 % frequency deviation (melody) e 1.5 ? + 1.5 % tone output dc level 0.45 0.50 0.55 vdd high group pre-emphasis 1 2.15 3 db total harmonic distortion ? e25 ? db table 10-9 square wave tones at tno characteristic min. typ. max. unit operating voltage 2.7 ? 5.5 v tone output level: low group e row high group e column ? ? 0.270 0.360 ? ? v p-p v p-p frequency deviation (melody) e 1.5 ? + 1.5 % tone output dc level (+ 1/2 v p-p value) 0.45 0.50 0.55 vdd tpg 99 05f4book page 7 tuesday, august 5, 1997 1:10 pm
motorola 10-8 MC68HC05F4 electrical specifications 10 10.7 eeprom additional information table 10-10 tonex at tnx output characteristic min. typ. max. unit operating voltage 2.7 ? 5.5 v tone output level (square wave) ? v dd ?v p-p frequency deviation e 1.5 ? + 1.5 % table 10-11 eeprom additional information temperature read/write cycles remarks 0 c e 85 c 10 000 the value is regularly tested and monitored 50 c 35 000 this value is predicted from the tested ones 25 c 100 000 this value is predicted from the tested ones tpg 100 05f4book page 8 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 11-1 mechanical data 11 11 mechanical data figure 11-1 44-pin qfp pinout pb6 pb7 pc7 12 13 15 16 17 18 19 20 21 22 14 tcmp2 tnx tno pc2 pa0 pc1 pa1 pc0 pa2 pa5 pa6 pd0 pd1 pd2 pd3 vss osc2 osc1 pa7 tcap2 tcmp1 pc3 pc4 pc5 pc6 vdd tcap1 1 2 4 5 6 7 8 9 10 11 3 pd4 44 43 41 40 39 38 36 35 34 42 37 pa3 pa4 33 32 31 30 29 28 27 26 25 pb5 pb4 pd7 pb2 pd6 pb1 pd5 pb0 irq reset pb3 24 23 tpg 101 05f4book page 1 tuesday, august 5, 1997 1:10 pm
motorola 11-2 MC68HC05F4 mechanical data 11 figure 11-2 44-pin qfp mechanical dimensions 44 lead qfp 0.20 m c a e b s d s l 23 12 - b - b v 0.05 a e b - d - a s 0.20 m h a e b s d s l - a - detail a b b - a, b, d - p detail a f n j d section beb base metal g h e c -c- m detail c m -h- datum plane seating plane u t r q k w x dim. min. max. notes dim. min. max. a 9.90 10.10 1. datum plane ehe is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 2. datums aeb and ed to be determined at datum plane ehe. 3. dimensions s and v to be determined at seating plane ece. 4. dimensions a and b do not include mould protrusion. allowable mould protrusion is 0.25mm per side. dimensions a and b do include mould mismatch and are determined at datum plane ehe. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. 6. dimensions and tolerancing per ansi y 14.5m, 1982. 7. all dimensions in mm. m5 10 b 9.90 10.10 n 0.130 0.170 c 2.10 2.45 q 0 7 d 0.30 0.45 r 0.13 0.30 e 2.00 2.10 s 12.95 13.45 f 0.30 0.40 t 0.13 ? g 0.80 bsc u 0 ? h ? 0.250 v 12.95 13.45 j 0.130 0.230 w 0.40 ? k 0.65 0.95 x 1.6 ref l 8.00 ref 0.20 m c a e b s d s 0.05 a e b 0.20 m h a e b s d s 0.20 m c a e b s d s case no. 824a-01 22 33 34 44 111 tpg 102 05f4book page 2 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 11-3 mechanical data 11 figure 11-3 28-pin pdip/soic pinout 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 tcap1 tcmp1 tcap2 tcmp2 tnx tno pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vdd pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 irq reset osc1 osc2 vss tpg 103 05f4book page 3 tuesday, august 5, 1997 1:10 pm
motorola 11-4 MC68HC05F4 mechanical data 11 figure 11-4 28-pin soic mechanical dimensions g d 28 pl c k e t e seating plane m f j 0.25 m b m 0.25 m b s a s t 14 pl r x 45 1 dim. min. max. notes dim. min. max. a 17.80 18.05 1. dimensions ?a? and ?b? are datums and ?t? is a datum surface. 2. dimensioning and tolerancing per ansi y14.5m, 1982. 3. all dimensions in mm. 4. dimensions ?a? and ?b? do not include mould protrusion. 5. maximum mould protrusion is 0.15 mm per side. j 0.229 0.317 b 7.40 7.60 k 0.127 0.292 c 2.35 2.65 m 0 8 d 0.35 0.49 p 10.05 10.55 f 0.41 0.90 r 0.25 0.75 g 1.27 bsc ? ? ? case 751f-03 e a e e b e p tpg 104 05f4book page 4 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 11-5 mechanical data 11 figure 11-5 mechanical dimensions for 28-pin pdip package dim. min. max. notes dim. min. max. a 36.45 37.21 1. all dimensions in mm. 2. positional tolerance of leads (?? shall be within 0.25 mm at maximum material condition, in relation to seating plane and to each other. 3. dimension ??is to centre of leads when formed parallel. 4. dimension ??does not include mould protrusion. h 1.65 2.16 b 13.72 14.22 j 0.20 0.38 c 3.94 5.08 k 2.92 3.43 d 0.36 0.56 l 15.24 bsc f 1.02 1.52 m 0 15 g 2.54 bsc n 0.51 1.02 g 1 f d h c n k l m j case 710 b a seating plane tpg 105 05f4book page 5 tuesday, august 5, 1997 1:10 pm
motorola 11-6 MC68HC05F4 mechanical data this page left blank intentionally 11 tpg 106 05f4book page 6 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola 12-1 ordering information 12 12 ordering information this section describes the information needed to order the MC68HC05F4. to initiate a rom pattern for the mcu, it is necessary to ?st contact your local ?ld service of?e, local sales person or motorola representative. please note that you will need to supply details such as: mask option selections; temperature range; oscillator frequency; package type; electrical test requirements; and device marking details so that an order can be processed, and a customer speci? part number allocated. refer to table 12-1 for appropriate part numbers. table 12-1 mc order numbers device title package type temperature part number MC68HC05F4 44-pin qfp 0 to 70 c MC68HC05F4fb 28-pin soic MC68HC05F4dw 28-pin dip MC68HC05F4p MC68HC05F4 44-pin qfp e40 to 85 c MC68HC05F4cfb 28-pin soic MC68HC05F4cdw 28-pin dip MC68HC05F4cp mc68hc705f4 44-pin qfp 0 to 70 c mc68hc705f4fb 28-pin soic mc68hc705f4dw 28-pin dip mc68hc705f4p tpg 107 05f4book page 1 tuesday, august 5, 1997 1:10 pm
motorola 12-2 MC68HC05F4 ordering information 12 12.1 eproms for the MC68HC05F4, a 16k byte eprom programmed with the customers software (positive logic for address and data) should be submitted for pattern generation. all unused bytes should be programmed to $00. the eprom should be clearly labelled, placed in a conductive ic carrier and securely packed. 12.2 veri?ation media all original pattern media (eproms) are ?ed for contractual purposes and are not returned. a computer listing of the rom code will be generated and returned with a listing veri?ation form. the listing should be thoroughly checked and the veri?ation form completed, signed and returned to motorola. the signed veri?ation form constitutes the contractual agreement for creation of the custom mask. if desired, motorola will program blank eproms (supplied by the customer) from the data ?e used to create the custom mask, to aid in the veri?ation process. 12.3 rom veri?ation units(rvu) ten mcus containing the customers rom pattern will be provided for program veri?ation. these units will have been made using the custom mask but are for rom veri?ation only. for expediency, they are usually unmarked and are tested only at room temperature (25 c) and at 5 volts. these rvus are included in the mask charge and are not production parts. they are neither backed nor guaranteed by motorola quality assurance. tpg 108 05f4book page 2 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola a-1 a a features specific to the mc68hc705f4 the mc68hc705f4 is the eprom version of the MC68HC05F4, having 7679 bytes of eprom plus 367 bytes of bootloader rom. it has the same amount of ram, eeprom, i/o, and user vectors. it also has the same on-board peripherals as the MC68HC05F4. a.1 features 7680 bytes of user eprom plus 16 bytes of user vectors 368 bytes of bootloader rom available in 44-pin qfp package, 28-pin soic package and 28-pin pdip package (ports c and d not available in 28-pin packages) a.2 memory and registers the mc68hc705f4 has a 16k byte memory map consisting of registers (for i/o, control and status), user ram, user rom, eeprom, bootloader rom and reset and interrupt vectors as shown in figure a-2 . a.2.1 registers all the i/o, control and status registers of the mc68hc705f4 are contained within the ?st 64 byte block of the memory map, as detailed in table a-1 . tpg 109 05f4book page 1 tuesday, august 5, 1997 1:10 pm
motorola a-2 MC68HC05F4 a figure a-1 mc68hc705f4 block diagram pd7 pd6 pd5 pd4 pd2 pd1 pd0 pd3 port d ? dtmf & 16-bit timer tcmp2 tcap2 tcmp1 tcap1 port b port a port c ? pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 vdd vss 256 bytes user eeprom 256 bytes ram m68hc05 cpu keyboard interrupt 368 bytes bootloader rom 7680 bytes user eprom 16 bytes user vectors core timer cop melody generator osc1 osc2 ceramic oscillator and divider reset irq tno tnx ? note that ports c and d are only available with the 44-pin package. tpg 110 05f4book page 2 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola a-3 a figure a-2 mc68hc705f4 memory map $00 port a data (porta) $0000 bootloader rom (368 bytes) user eprom (7680 bytes) unused eeprom (256 bytes) ram (384 bytes) unused i/o (64 bytes) $0040 $0200 $02ff $3000 $3f00 $3ff0 $3fff mc68hc705f4 stack user vectors (16 bytes) $01 port b data (portb) $02 port c data 1 (portc) $03 port d data 1 (portd) $04 port a ddr (ddra) $05 port b ddr (ddrb) $06 port c ddr 1 (ddrc) $08 core time control/status (ctcsr) $09 core timer counter (ctcr) $0a unused $0b reserved $0c reserved $0d dtmf row fequency counter (fcr) $0e dtmf column fequency counter (fcc) $0f dtmf tone control (tncr) $10 key control (kcr) $11 system options (sor) $12e$1b unused $1c eeprom programming (eeprog) $1e unused $1f reserved $20 capture 1 high (icr1h) $21 capture 1 low (icr1l) $22 compare 1 high (ocr1h) $23 compare 1 low (ocr1l) $24 capture 2 high (icr2h) $25 capture 2 low (icr2l) $26 compare 2 high (ocr2h) $27 compare 2 low (ocr2l) $28 timer counter high (cnth) $29 timer counter low (cntl) $2a alternate counter high (acnth) $2b alternate counter low (acntl) $2c timer control 1 (tcr1) $2d timer control 2 (tcr2) $2e timer status (tsr) $2fe$3f unused $07 port d ddr 1 (ddrd) $0140 $00c0 $00ff 1. not available in 28-pin package. $1d eprom programming (eprog) tpg 111 05f4book page 3 tuesday, august 5, 1997 1:10 pm
motorola a-4 MC68HC05F4 a table a-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 undetned port b data (portb) $0001 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 undetned port c data (portc) (1) $0002 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 undetned port d data (portd) (1) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 undetned port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) (1) ) $0006 0000 0000 port d data direction ((ddrd) (1) $0007 0000 0000 core timer control/status (ctcsr) $0008 ctof rtif ctofe rtie rtof rrtif rt1 rt0 uu00 0011 core timer counter (ctcr) $0009 0000 0000 dtmf row freq. control (fcr) $000d 0 0 0 fcr4 fcr3 fcr2 fcr1 fcr0 undetned dtmf column freq. control (fcc) $000e 0 0 0 fcc4 fcc3 fcc2 fcc1 fcc0 undetned dtmf tone control (tncr) $000f ms1 ms0 tger tgec tnoe 0 0 0 0000 0000 key control (kcr) $0010 kf kie 000000 0000 0000 system options (sor) $0011 lvif lvie lvion sc irq 0 0 0 0000 0000 eeprom programming (eeprog) $001c 0 cpen 0 er1 er0 latch eerc eepgm 0000 0000 eprom programming (eprog) $001d 0 0 0 ts1 ts0 elatch 0 epgm 0000 0000 input capture 1 high (icr1h) $0020 (bit 15) (bit 8) undetned input capture 1 low (icr1l) $0021 undetned output compare 1 high (ocr1h) $0022 (bit 15) (bit 8) undetned output compare 1 low (ocr1l) $0023 undetned input capture 2 high (icr2h) $0024 (bit 15) (bit 8) undetned input capture 2 low (icr2l) $0025 undetned output compare 2 high (ocr2h) $0026 (bit 15) (bit 8) undetnd output compare 2 low (ocr2l) $0027 undetned tpg 112 05f4book page 4 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola a-5 a a.2.2 eprom the mc68hc705f4 has 7680 bytes of eprom located from $2000 to $3dff, plus 16 bytes of user vectors from $3ff0 to $3fff. up to 4 bytes of eprom can be programmed simultaneously by correctly manipulating the bits in the eprom programming register. a.2.2.1 eprom programming register (prog) epgm ?eprom program control 1 (set) programming power connected to the eprom array. 0 (clear) programming power disconnected from the eprom array. elatch and epgm cannot be set on the same write operation. epgm can only be set if elatch is set. epgm is automatically cleared when elatch is cleared. elatch ?eprom latch control 1 (set) eprom address and data buses con?ured for programming. 0 (clear) eprom address and data buses con?ured for normal reads (1) not available in 28-pin packages timer counter high (cnth) $0028 (bit 15) (bit 8) 1111 1111 timer counter low (cntl) $0029 1111 1100 alternate counter high (acnth) $002a (bit 15) (bit 8) 1111 1111 alternate counter low (acntl) $002b 1111 1100 timer control 1 (tcr1) $002c ici1e ici2e oci1e toie co1e iedg1 iedg2 olvl1 0000 0uu0 timer control 2 (tcr2) $002d 0 0 oci2e 0 co2e 0 0 olvl2 0000 0000 timer status (tsr) $002e ic1f ic2f oc1f tof tcap1 tcap2 oc2f 0 uuuu uuu0 u = undetned address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eprom programming (prog) $001d 00000 elatch 0 epgm 0000 0000 table a-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset tpg 113 05f4book page 5 tuesday, august 5, 1997 1:10 pm
motorola a-6 MC68HC05F4 a elatch causes address and data buses to be latched when a write to eprom is carried out. the eprom cannot be read if elatch = 1. this bit should not be set unless a programming voltage is applied to the vpp pin. a.2.2.2 eprom programming operation the following steps should be taken to program a byte of eprom: 1) apply the programming voltage v pp to the irq pin. 2) set the elatch bit. 3) write to the eprom address. 4) set the epgm bit for a time t epgm to apply the programming voltage. 5) clear the elatch bit. if the address bits a13?2 do not change, i.e. all bytes are located within the same 4 byte address block, then multibyte programming is permitted. the multibyte programming facility allows up to 4bytes of data to be written to the desired addresses after the elatch bit has been set. a.3 electrical speci?ations this section gives the electrical speci?ations for the mc68hc705f4, the eprom version of the MC68HC05F4. contained in this section is the information speci? to the mc68hc705f4 which differs from that detailed in section 10 . a.3.1 eprom characteristics table a-2 eprom characteristics characteristic symbol value unit eprom programming voltage rate v pp v ss e 0.3 to +17 + 0.5 v eprom programming voltage v pp typ. 16.0 min. 15.5 e max. 16.5 v eprom programming time t epgm min. 4.0 ms tpg 114 05f4book page 6 tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola i glossary glossary this section contains abbreviations and specialist words used in this data sheet and throughout the industry. further information on many of the terms may be gleaned from motorolas m68hc11 reference manual, m68hc11rm/ad , or from a variety of standard electronics text books. $xxxx the digits following the ? are in hexadecimal format. %xxxx the digits following the ? are in binary format. a/d , adc analog-to-digital (converter). bootstrap mode in this mode the device automatically loads its internal memory from an external source on reset and then allows this program to be executed. byte eight bits. ccr condition codes register; an integral part of the cpu. cerquad a ceramic package type, principally used for eprom and high temperature devices. clear ? ?the logic zero state; the opposite of ?et? cmos complementary metal oxide semiconductor. a semiconductor technology chosen for its low power consumption and good noise immunity. cop computer operating properly. aka ?atchdog? this circuit is used to detect device runaway and provide a means for restoring correct operation. cpu central processing unit. d/a, dac digital-to-analog (converter). eeprom electrically erasable programmable read only memory. aka ?erom? eprom erasable programmable read only memory. this type of memory requires exposure to ultra-violet wavelengths in order to erase previous data. aka ?rom? esd electrostatic discharge. expanded mode in this mode the internal address and data bus lines are connected to external pins. this enables the device to be used in much more complex systems, where there is a need for external memory for example. tpg 117 05f4book page i tuesday, august 5, 1997 1:10 pm
motorola ii MC68HC05F4 glossary evs evaluation system. one of the range of platforms provided by motorola for evaluation and emulation of their devices. hcmos high-density complementary metal oxide semiconductor. a semiconductor technology chosen for its low power consumption and good noise immunity. i/o input/output; used to describe a bidirectional pin or function. input capture (ic) this is a function provided by the timing system, whereby an external event is ?aptured by storing the value of a counter at the instant the event is detected. interrupt this refers to an asynchronous external event and the handling of it by the mcu. the external event is detected by the mcu and causes a predetermined action to occur. irq interrupt request. the overline indicates that this is an active-low signal format. k byte a kilo-byte (of memory); 1024 bytes. lcd liquid crystal display. lsb least signi?ant byte. m68hc05 motorolas family of 8-bit mcus. mcu microcontroller unit. mi bus motorola interconnect bus. a single wire, medium speed serial communications protocol. msb most signi?ant byte. nibble half a byte; four bits. nrz non-return to zero. opcode the opcode is a byte which identi?s the particular instruction and operating mode to the cpu. see also: prebyte, operand. operand the operand is a byte containing information the cpu needs to execute a particular instruction. there may be from 0 to 3 operands associated with an opcode. see also: opcode, prebyte. output compare (oc) this is a function provided by the timing system, whereby an external event is generated when an internal counter value matches a prede?ed value. plcc plastic leaded chip carrier package. pll phase-locked loop circuit. this provides a method of frequency multiplication, to enable the use of a low frequency crystal in a high frequency circuit. prebyte this byte is sometimes required to qualify an opcode, in order to fully specify a particular instruction. see also: opcode, operand. tpg 118 05f4book page ii tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola iii glossary pull-down, pull-up these terms refer to resistors, sometimes internal to the device, which are permanently connected to either ground or v dd . pwm pulse width modulation. this term is used to describe a technique where the width of the high and low periods of a waveform is varied, usually to enable a representation of an analog value. qfp quad ?t pack package. ram random access memory. fast read and write, but contents are lost when the power is removed. rfi radio frequency interference. rti real-time interrupt. rom read-only memory. this type of memory is programmed during device manufacture and cannot subsequently be altered. rs-232c a standard serial communications protocol. sar successive approximation register. sci serial communications interface. set ? ?the logic one state; the opposite of ?lear? silicon glen an area in the central belt of scotland, so called because of the concentration of semiconductor manufacturers and users found there. single chip mode in this mode the device functions as a self contained unit, requiring only i/o devices to complete a system. spi serial peripheral interface. test mode this mode is intended for factory testing. ttl transistor-transistor logic. uart universal asynchronous receiver transmitter. vco voltage controlled oscillator. watchdog see ?op? wired-or a means of connecting outputs together such that the resulting composite output state is the logical or of the state of the individual outputs. word two bytes; 16 bits. xirq non-maskable interrupt request. the overline indicates that this has an active-low signal format. tpg 119 05f4book page iii tuesday, august 5, 1997 1:10 pm
motorola iv MC68HC05F4 glossary this page left blank intentionally tpg 120 05f4book page iv tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola i index index in this index numeric entries are placed ?st; page references in italics indicate that the reference is to a ?ure. 28-pin pdip mechanical dimensions 11? pinout 11? 28-pin soic mechanical dimensions 11? 44-pin qfp mechanical dimensions 11? pinout 11? a a ?accumulator 9? addressing modes 9? 9?3 alternate counter register 6? b bit set/clear addressing mode 9?3 bit test and branch addressing mode 9?3 block diagrams core timer 5? MC68HC05F4 1? mc68hc705f4 a-2 programmable timer 6? c c-bit in ccr 9? ccr ?condition code register 9? clocks ?see oscillator clock co1e bit in tcr1 6? co2e bit in tcr2 6? control timing 10? , 10? cop 8? cop watchdog timer 5? cop reset times 5? core timer block diagram 5? ctcr ?counter register 5? ctcsr ?control/status register 5? during stop mode 5? during wait mode 5? interrupts 5? , 8? counter alternate counter register 6? counter register 6? programmable timer 6? cpen-bit in eprog 3? cpu a ?accumulator 9? addressing modes 9? 9?3 ccr ?condition code register 9? instruction set 9? 9?1 pc ?program counter 9? programming model 9? sp ?stack pointer 9? stacking order 9? x ?index register 9? crystal 2? ctcr ?core timer counter register 5? ctcsr ?core timer control/status register ctof ?core timer overflow 5? ctofe?core timer overflow enable 5? rt1, rt0 real time interrupt rate select 5? rtie ?real time interrupt enable 5? rtif ?real time interrupt flag 5? d dc characteristics 10? , 10? direct addressing mode 9? dmg registers fcc ?column frequency control register 7? fcr ?row frequency control register 7? tncr ?tone control register 7? dtmf/melody generator (dmg) during stop mode 7? during wait mode 7? features 7? operation 7? tpg 121 05f4book page i tuesday, august 5, 1997 1:10 pm
motorola ii MC68HC05F4 index e eepgm-bit in eprog 3? eeprom 3? eprog ?eeprom programing register 3? erase modes 3? erasing procedures 3? latch - latch bit 3? programming procedures 3? sample programming sequence 3? eerc-bit in eprog 3? elatch bit in prog a-5 electrical specifications control timing (2.5v) 10? control timing (5v) 10? dc characteristics (2.5v) 10? dc characteristics (5v) 10? dtmf/melody generator 10? eprom characteristics a-6 maximum ratings 10? thermal characteristics 10? epgm bit in prog a-5 eprog ?eeprom programing register 3? eprom multibyte programming a-6 prog ?eprom programming register a-5 programming a-6 er1, er0 bits in eprog 3? extended addressing mode 9?2 external clock 2? f fcc ?column frequency control register 7? fcr ?row frequency control register 7? features mc68hc05f32 1? mc68hc705f4 a-1 flowcharts interrupt 8? stop and wait 2? h h-bit in ccr 9? i i/o port structure 4? i/o ports i/o port structure 4? port a 4? port b 4? port c 4? port d 4? programming 4? i-bit in ccr 9? ic1f, ic2f bits in tsr 6? ic1ie bit in tcr 6? ic2ie bit in tcr1 6? icr1 ?input capture register 6? iedg1 bit in tcr1 6? iedg2 bit in tcr1 6? illegal address reset 8? immediate addressing mode 9? indexed addressing modes 9?2 inherent addressing mode 9? input capture 6? instruction set 9? 9?1 tables of instructions 9? 9?1 interrupts 8? core timer 8? hardware 8? interrupt flowchart 8? keyboard 8? maskable 8? nonmaskable 8? priorities 8? programmable timer 8? real-time 5? , 8? software (swi) 8? irq 2? irq bit in sor 2? k key control register kf ?keyboard interrupt status flag 4? kie ?keyboard interrupt enable 4? keyboard interrupt 4? , 8? l latch-bit in eprog 3? low power modes 2? reset, stop, wait ?as interrupt sequence 8? stop 2? wait 2? lvie bit in sor 2? , 8? lvif bit in sor 2? , 8? lvion bit in sor 2? , 8? m mask options 1? maximum ratings 10? mc68hc05f32 features 1? mask options 1? MC68HC05F4 block diagram 1? mc68hc705f4 tpg 122 05f4book page ii tuesday, august 5, 1997 1:10 pm
MC68HC05F4 motorola iii index block diagram a-2 features a-1 memory bootloader rom 3? eeprom 3? eprom a-5 memory map 3? , a-3 ram 3? rom 3? modes of operation low power modes 2? single-chip 2? n n-bit in ccr 9? o oc1ie bit in tcr1 6? oc2ie bit in tcr2 6? ocr1, ocr2 ?output compare registers 6?1 olvl1 bit in tcr1 6? olvl2 bit in tcr2 6? osc1, osc2 pins 2? oscillator clock connections 2? crystal 2? external clock 2? output compare 6?1 p packages 28-pin pdip 11? 44-pin qfp 11? pc ?program counter 9? pins irq 2? osc1, osc2 2? pa0?a7 2? pb0?b7 2? pc0?c7 2? pd0?d7 2? reset 2? , 8? tcap1, tcap2, tcmp1, tcmp2 2? tno, tnx 2? vdd, vss 2? por ?see power-on reset port a 4? keyboard interrupt 4? port b 4? port c 4? port d 4? port registers data direction registers 4? port data registers 4? power-on reset 8? prog ?eprom programming register a-5 elatch ?eprom latch control a-5 epgm ?eprom program control a-5 programmable timer block diagram 6? counter 6? during stop mode 6?3 during wait mode 6?3 icr1 6? interrupts 8? ocr1, ocr2 6?1 tcr1, tcr2 6? timing diagrams 6?3 tsr 6? programming eeprom 3? eprom a-6 r real-time interrupts 5? , 8? example rti periods 5? register summary 3? , a-4 relative addressing mode 9?3 reset 2? resets 8? cop 8? illegal address 8? power-on reset 8? reset pin 2? , 8? rt1, rt0 bits in ctcsr 5? rtie bit in ctcsr 5? rtif bit in ctcsr 5? s sc bit in sor 2? sor ?system options register 2? , 8? irq ?interrupt sensitivity 2? lvie ?low voltage interrupt enable 2? , 8? lvif ?low voltage interrupt flag 2? , 8? lvion ?low voltage interrupt on 2? , 8? sc ?system clock option 2? sp ?stack pointer 9? stop mode 2? swi ?see interrupts system options register 2? , 8? t tcr1 ?timer control register 1 6? co1e ?compare output enable bit 1 6? ic1ie ?input capture interrupt enable 1 6? ic2ie ?input capture interrupt enable 2 6? tpg 123 05f4book page iii tuesday, august 5, 1997 1:10 pm
motorola iv MC68HC05F4 index iedg1 ?input edge bit 1 6? iedg2 ?input edge bit 2 6? oc1ie ?output compare interrupt enable 1 6? olvl1 ?output level bit 1 6? toie ?timer overflow interrupt enable 6? tcr2 ?timer control register 2 6? co2e ?compare output enable bit 2 6? oc2ie ?output compare interrupt enable 2 6? olvl2 ?output level bit 2 6? thermal characteristics 10? timing diagrams programmable timer 6?3 tncr ?tone control register ms1, ms0 ?melody select for operation 7? tgec ?tone generator enable column path 7? tger ?tone generator enable row path 7? tnoe ?tone output enable 7? tno, tnx pins 2? tnoe bit in tncr 7? tof bit in tsr 6? toie bit in tcr1 6? tsr ?timer status register 6? ic1f, ic2f ?input capture flags 6? oc1f, oc2f ?output compare flags 6? tof ?timer overflow status flag 6? v vdd 2? vss 2? w wait mode 2? watchdog timer 8? x x ?index register 9? z z-bit in ccr 9? tpg 124 05f4book page iv tuesday, august 5, 1997 1:10 pm
customer feedback questionnaire (mc68hc05e6/d) motorola wishes to continue to improve the quality of its documentation. we would welcome your feedback on the publication you have just received. having used the document, please complete this card (or a photocopy of it, if you prefer). 1. how would you rate the quality of the document? check one box in each category. excellent poor excellent poor organization oooo tables oooo readability oooo table of contents oooo understandability oooo index oooo accuracy oooo page size/binding oooo illustrations oooo overall impression oooo comments: 2. what is your intended use for this document? if more than one option applies, please rank them (1, 2, 3). selection of device for new application o other o please specify: system design o training purposes o 3. how well does this manual enable you to perform the task(s) outlined in question 2? completely not at all comments: oooo 4. how easy is it to ?d the information you are looking for? easy dif?ult comments: oooo 5. is the level of technical detail in the following sections suf?ient to allow you to understand how the device functions? too little detail too much detail 6. have you found any errors? if so, please comment: 7. from your point of view, is anything missing from the document? if so, please say what: ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ?cut along this line to remove section 1 introduction section 2 modes of operation and pin descriptions section 3 memory and registers section 4 parallel input/output ports section 5 core timer section 6 16-bit programmable timer section 7 dtmf/melody generator section 8 resets and interrupts section 9 cpu core and instruction set section 10 electrical specifications section 11 mechanical data section 12 ordering information appendixa features specific to the mc68hc705f4 125 05f4book page v tuesday, august 5, 1997 1:10 pm
13. currently there is some discussion in the semiconductor industry regarding a move towards providing data sheets in electron ic form. if you have any opinion on this subject, please comment. 14. we would be grateful if you would supply the following information (at your discretion), or attach your card. name: phone no: position: fax no: department: company: address: thank you for helping us improve our documentation, graham livey, technical publications manager, motorola ltd., scotland . ?cut along this line to remove ?third fold back along this line 8. how could we improve this document? 9. how would you rate motorolas documentation? excellent poor ?in general oooo ?against other semiconductor suppliers oooo 10. which semiconductor manufacturer provides the best technical documentation? 11. which company (in any ?ld) provides the best technical documentation? 12. how many years have you worked with microprocessors? less than 1 year o 1? years o 3? years o more than 5 years o ?second fold back along this line ? finally, tuck this edge into opposite ?p " by air mail par avion ne pas affranchir ibrs number phq-b/207/g ccri numero phq-b/207/g reponse payee grande-bretagne motorola ltd., colvilles road, kelvin industrial estate, east kilbride, g75 8br. great britain. f.a.o. technical publications manager (re: mc68hc05e6/d) no stamp required ?first fold back along this line !motorola semiconductor products sector 126 05f4book page vi tuesday, august 5, 1997 1:10 pm
1 2 3 4 5 6 7 8 9 10 11 12 a introduction modes of operation and pin descriptions memory and registers parallel input/output ports core timer 16-bit programmable timer dtmf/melody generator resets and interrupts cpu core and instruction set electrical specifications mechanical data ordering information features specific to the mc68hc705f4 tpg 127 05f4book page 7 tuesday, august 5, 1997 1:10 pm
1 2 3 4 5 6 7 8 9 10 11 12 a introduction modes of operation and pin descriptions memory and registers parallel input/output ports core timer 16-bit programmable timer dtmf/melody generator resets and interrupts cpu core and instruction set electrical specifications mechanical data ordering information features specific to the mc68hc705f4 tpg 128 05f4book page 8 tuesday, august 5, 1997 1:10 pm

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